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參數(shù)資料
| 型號： | AD8303ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SERIAL 14SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD8303 Obsolescence 15/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 14µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 9.6mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | * |
| 其它名稱： | AD8303ARZ-REELDKR |
AD8303
REV. 0
–5–
Table I. Control-Logic Truth Table
CS
CLK RS
MSB
SHDN LDA/B
Serial Shift Register Function
DAC Register Function
H
X
H
X
H
No Effect
Latched
L
H
X
H
No Effect
Latched
L
H
X
H
No Effect
Latched
L
↑+
H
X
H
Shift-Register-Data Advanced One Bit Latched
↑+
L
H
X
H
No Effect
Latched
HX
H
X
H
↓–
No Effect
Updated with Current Shift Register Contents
H
X
H
X
H
L
No Effect
Transparent
X
L
H
X
No Effect
Loaded with 800H
XX
↑+
H
No Effect
Latched with 800H
X
L
H
X
No Effect
Loaded with All Zeros
XX
↑+
X
H
No Effect
Latched All Zeros
X
L
X
No Effect
NOTES
1
↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
2Do not clock in serial data while LDA or LDB is LOW.
PIN DESCRIPTIONS
Pin No.
Name
Function
1
AGND
Analog Ground.
2VOUTA
DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference
maintains a fixed full-scale voltage independent of time, temperature and power supply variations.
3VREF
Reference Voltage Output Terminal. Very high output resistance must be buffered if used as a virtual
ground.
4
DGND
Digital Ground
5
CS
Chip Select, Active Low Input. Disables shift register loading when high. Does not effect LDA or LDB
operation.
6
CLK
Clock Input, positive edge clocks data into shift register.
7
SDI
Serial Data Input, input data loads directly into the shift register.
8
LDA
Load DAC register strobes, active low. Transfers shift register data to DAC A register. Asynchronous active
low input. See Control Logic Truth Table for operation.
9
RS
Resets DAC register to zero condition or half-scale depending on MSB pin. Asynchronous active low input.
10
LDB
Load DAC register strobes, active low. Transfers shift register data to DAC B register. Asynchronous active
low input. See Control Logic Truth Table for operation.
11
MSB
Digital Input: Logic High presets DAC registers to half-scale 800H (sets MSB bit to one) when the RS pin
is strobed; Logic Low clears all DAC registers to zero (000H) when the RS pin is strobed.
12
SHDN
Active low shutdown control input. Does not affect register contents as long as power is present on VDD.
13
VDD
Positive power supply input. Specified range of operation +2.7 V to +5.5 V
14
VOUTB
DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference
maintains a fixed full-scale voltage independent of time, temperature and power supply variations.
PIN CONFIGURATION
14-Pin P-DIP (N-14)
14-Lead SOIC (R-14)
14
13
12
11
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AGND
MSB
SHDN
VDD
VOUTB
VOUTA
VREF
DGND
AD8303
LDA
RS
LDB
CS
CLK
SDI
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| AD8303JRU | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 12-bit 14-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:IC,DUAL 12BIT,+3V,COMPLETE DAC - Bulk |
| AD8303JRU-REEL | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 12-bit 14-Pin TSSOP T/R |
| AD8303JRUZ | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 12-bit 14-Pin TSSOP |
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