參數(shù)資料
型號(hào)： AD8196ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/24頁(yè)
文件大?。?/td> 0K
描述： IC SWITCH DVI/HDMI 2:1 56-LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： HDMI/DVI 開(kāi)關(guān)
應(yīng)用： DVI，HDMI 信號(hào)開(kāi)關(guān)
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤(pán)
AD8196
Rev. 0 | Page 12 of 24
THEORY OF OPERATION
INTRODUCTION
The AD8196 is a pin-to-pin HDMI 1.3 receive-compliant
replacement for the AD8190. The primary function of the
AD8196 is to switch one of two (DVI or HDMI) single link
sources to one output. Each HDMI/DVI link consists of four
differential, high speed channels and four auxiliary single-
ended, low speed control signals. The high speed channels
include a data-word clock and three transition minimized
differential signaling (TMDS) data channels running at 10×
the data-word clock frequency for data rates up to 2.25 Gbps.
The four low speed control signals are 5 V tolerant bidirectional
lines that can carry configuration signals, HDCP encryption,
and other information, depending upon the specific application.
All four high speed TMDS channels in a given link are identical;
that is, the pixel clock can be run on any of the four TMDS
channels. Transmit and receive channel compensation is provided
for the high speed channels where the user can (manually) select
among a number of fixed settings.
The AD8196 has I2C serial programming with two user pro-
grammable I2C slave addresses. The I2C slave address of the
AD8196 is 0b100100X. The least significant bit, represented by
X in the address, is set by tying the I2C_ADDR pin to either
3.3 V (for the value, X = 1) or to 0 V (for X = 0).
INPUT CHANNELS
Each high speed input differential pair terminates to the
3.3 V VTTI power supply through a pair of single-ended 50 Ω
on-chip resistors, as shown in Figure 25. The input terminations
can be optionally disconnected for approximately 100 ms following
a source switch. The user can program which of the eight high
speed input channels employs this feature by selectively pro-
gramming the associated RX_PT bits in the input termination
pulse register. Additionally, all the input terminations can be
disconnected by programming the RX_TO bit in the receiver
settings register. By default, the input termination is enabled.
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually control the equalization level of the eight high
speed input channels by selectively programming the associated
RX_EQ bits in the receive equalizer register. No specific cable
length is suggested for a particular equalization setting because
cable performance varies widely between manufacturers;
however, in general, the equalization of the AD8196 can be set
to 12 dB without degrading the signal integrity, even for short
input cables. At the 12 dB setting, the AD8196 can equalize
more than 20 meters of 24 AWG cable at data rates of 2.25 Gbps.
CABLE
EQ
50
IP_xx
IN_xx
AVEE
VTTI
0
64
70
-02
5
Figure 25. High Speed Input Simplified Schematic
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two single-ended 50 Ω
on-chip resistors (see Figure 26). This output termination is
user-selectable; all the output terminations can be turned on
or off by programming the TX_PTO bit of the transmitter
settings register.
VTTO
50
OPx
ONx
AVEE
DISABLE
IOUT
0
64
70
-02
6
Figure 26. High Speed Output Simplified Schematic
The output termination resistors of the AD8196 back-terminate
the output TMDS transmission lines. These back-terminations,
as recommended in the HDMI 1.3 specification, act to absorb
reflections from impedance discontinuities on the output traces,
improving the signal integrity of the output traces and adding
flexibility to how the output traces can be routed. For example,
interlayer vias can be used to route the AD8196 TMDS outputs
on multiple layers of the PCB without severely degrading the
quality of the output signal.
The AD8196 output has a disable feature that places the outputs
in a tristate mode. This mode is enabled by programming the
HS_EN bit of the high speed device modes register. Larger wire-
OR’ed arrays can be constructed using the AD8196 in this mode.
The AD8196 requires output termination resistors when the
high speed outputs are enabled. Termination can be internal
and/or external. The internal terminations of the AD8196 are
enabled by programming the TX_PTO bit of the transmitter
settings register (the default upon reset). External terminations
can be provided either by on-board resistors or by the input
termination resistors of an HDMI/DVI receiver. If both the
internal terminations are enabled and external terminations are
present, set the output current level to 20 mA by programming
the TX_OCL bit of the transmitter settings register (the default
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