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參數(shù)資料
| 型號(hào)： | AD8177ABPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 21/40頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO CROSSPOINT SWIT 676BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 視頻交叉點(diǎn)開(kāi)關(guān) |
| 電路： | 3 x 16:5 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±2.5V |
| 電流 - 電源： | 460mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-BGA（27x27） |
| 包裝： | 管件 |
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AD8177
Rev. 0 | Page 28 of 40
06
60
5-
02
2
CMR
CMB
DIFF. R
DIFF. B
INPUT
OVERALL
CM
CMG
DIFF. G
CMENC
CMR
CMB
DIFF. R
DIFF. B
OUTPUT
OVERALL
CM
CMG
DIFF. G
VOCM_CMENCON
AD8177
Figure 49. AD8177 in Middle-of-Cat-5-Run Application, CM Encoding On
(Note that in this application, the H and V outputs,
though asserted, are not used.)
In this operation mode, the difference Δdiff = VBLK VOCM_
CMENCOFF still adds an output differential voltage, as described
Off section.
End-of-Cat-5-Run, CM Encoding Turned Off
In this application, each AD8177 output is tapped single-ended
at the positive phase and followed by a fast buffer to drive
a monitor at the end of a Cat-5 run (a suitable choice is the
AD8003 set up in a noninverting configuration with gain of +4).
The H and V outputs can then be used to drive the monitor
sync inputs directly. The relationship between the incoming
sync-on CM signaling and the H and V syncs is defined according
to Table 16.
Table 16. H and V Sync Truth Table (VPOS/VNEG = ±2.5 V)
CMR
CMG
CMB
H
V
0.5
0
Low
High
0
0.5
Low
0.5
0
High
Low
0
0.5
High
The following two statements are equivalent to the truth table
(see Table 16) in producing H and V for all allowable CM inputs:
H sync is high when the CM of Blue is larger than the CM
of Red.
V sync is high when the combined CM of Red and Blue is
larger than the CM of Green.
PROGRAMMING
The AD8177 has two options for changing the programming of
the crosspoint matrix. In the first option, a serial word of 45 bits
can be provided that updates the entire matrix each time. The
second option allows for changing the programming of a single
output via a parallel interface. The serial option requires fewer
signals, but more time (clock cycles) for changing the program-
ming; the parallel programming technique requires more
signals but allows for changing a single output at a time,
therefore requiring fewer clock cycles.
Serial Programming Description
The serial programming mode uses the device pins CS, CLK,
SERIN, UPDATE, and SER/PAR. The first step is to enable the
CLK by pulling CS low. Next, SER/PAR is pulled low to enable
the serial programming mode. The parallel clock WE should be
held high during the entire serial programming operation.
The UPDATE signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when UPDATE is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as defined
by the shifting data.
The data at SERIN is clocked in at every falling edge of CLK.
A total of 45 bits must be shifted in to complete the programming.
A total of five bits must be supplied for each of the five RGB
output channels: an output enable bit (D4) and four bits (D3
to D0) that determine the input channel. If D4 is low (output
disabled), the four associated bits (D3 to D0) do not matter
because no input is switched to that output. A sequence of five
bits at Logic 0 must be supplied in between each D4 to D0
group of bits for padding purposes. There are a total of four such
sequences of zeros.
The most significant output-address data is shifted in first, with
the enable bit (D4) shifted in first, followed by the input address
(D3 to D0) entered sequentially with D3 first and D0 last. The first
sequence of five bits at Logic 0 is shifted in next. Each remaining
output is programmed sequentially in a similar fashion, until
the least-significant-output-address data is shifted in. Note that
the last D4 to D0 group is not followed by a corresponding group
of five zeros. At this point, UPDATE can be taken low, which
causes the programming of the device according to the data that
was just shifted in. The UPDATE latches are asynchronous; and
when UPDATE is low, they are transparent.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8177-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD8178 | 制造商:AD 制造商全稱:Analog Devices 功能描述:450 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD8178ABPZ | 功能描述:IC VIDEO CROSSPOINT SWIT 676BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開(kāi)關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
| AD8178ABPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:450 MHz, Triple 16 】 5 Video Crosspoint Switch |
| AD8178-EVALZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:450 MHz, Triple 16 】 5 Video Crosspoint Switch |
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