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參數(shù)資料
| 型號： | AD80066KRSZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/21頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CTLR 16BIT 28SSOP |
| 標準包裝： | 1,500 |
| 類型： | 信號處理器 |
| 輸入類型： | 模擬 |
| 輸出類型： | 數(shù)字 |
| 接口： | 串行 |
| 電流 - 電源： | 95mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
AD80066
Rev. A | Page 19 of 20
APPLICATIONS INFORMATION
CIRCUIT AND LAYOUT RECOMMENDATIONS
Figure 23 shows the recommended circuit configuration for
4-channel CDS mode operation. The recommended input
coupling capacitor value is 0.1 μF (see the Analog Inputs—CDS
Mode section). A single ground plane is recommended for the
AD80066. A separate power supply can be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD80066.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC or by using external
digital buffers. To minimize the effect of digital transients
during major output code transitions, the falling edge of
CDSCLK2 should occur coincident with or before the rising
All 0.1 μF decoupling capacitors should be located as close as
possible to the AD80066 pins. When operating in 1-channel
mode, the unused analog inputs should be grounded.
Figure 24 shows the recommended circuit configuration for
4-channel SHA mode. All of the previously explained consid-
erations also apply to this configuration, except that the analog
input signals are directly connected to the AD80066 without the
use of coupling capacitors. Before connecting the signals, the
analog input signals must be dc-biased between 0 V and 1.5 V
or 3 V (see the Analog Inputs—SHA Mode section).
CLOCK
INPUTS
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD80066
AVDD
AVSS
A INPUT
DATA
INPUTS
3.3V
5V
SERIAL
INTERFACE
VINA
OFFSET
VINB
CML
VINC
CAPT
CAPB
VIND
AVSS
AVDD
SLOAD
SCLK
SDATA
CDSCLK1
CDSCLK2
ADCCLK
DRVDD
DRVSS
(MSB) D7
D6
D5
D4
D3
D2
D1
(LSB) D0
C INPUT
D INPUT
B INPUT
0.1F
1.0F
0.1F
10F
0.1F
0
85
52
-02
3
Figure 23. Recommended Circuit Configuration, 4-Channel CDS Mode
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
CLOCK
INPUTS
AVDD
DATA
INPUTS
3.3V
5V
CDSCLK1
CDSCLK2
ADCCLK
DRVDD
DRVSS
(MSB) D7
D6
D5
D4
D3
D2
D1
(LSB) D0
0.1F
TOP VIEW
(Not to Scale)
AD80066
A INPUT
5V
SERIAL
INTERFACE
C INPUT
D INPUT
B INPUT
0.1F
10F
0.1F
AVSS
VINA
OFFSET
VINB
CML
VINC
CAPT
CAPB
VIND
AVSS
AVDD
SLOAD
SCLK
SDATA
08
55
2-
02
4
Figure 24. Recommended Circuit Configuration, 4-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)
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