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參數(shù)資料
| 型號： | AD7944BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14B 2.5MSPS PULSR 20LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.5M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
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AD7944
Rev. A | Page 23 of 28
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7944 devices on
a 3-wire serial interface. It is available only in normal conversion
mode (TURBO is low). This feature is useful for reducing com-
ponent count and wiring connections, for example, in isolated
multiconverter applications or for systems with a limited inter-
facing capacity. Data readback is analogous to clocking a shift
register. A connection diagram example using two AD7944
devices is shown in Figure 34, and the corresponding timing is
given in Figure 35.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects chain mode,
and disables the busy indicator. In this mode, CNV is held high
during the conversion phase and the subsequent data readback.
When the conversion is complete, the MSB is output onto SDO,
and the AD7944 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
clocked by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 14 × N clocks are required to read back the N ADCs.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate and, consequently, more
AD7944 devices in the chain, provided that the digital host has
an acceptable hold time. The maximum conversion rate may be
reduced due to the total readback time.
CONVERT
DATA IN
CLK
DIGITAL HOST
AD7944
SDI
SDO
CNV
B
SCK
AD7944
SDI
SDO
CNV
A
SCK
TURBO
04658-
017
Figure 34. Chain Mode Without Busy Indicator Connection Diagram
TURBO = 0
SDOA = SDIB
DA13
DA12
DA11
SCK
1
2
3
26
27
28
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
12
13
tSCK
tSCKL
tSCKH
DA0
15
16
14
SDIA = 0
SDOB
DB13
DB12
DB11
DA1
DB1
DB0
DA13
DA12
tHSDO
tDSDO
tQUIET
tHSCKCNV
DA0
04658-
018
Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing
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