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參數(shù)資料
| 型號： | AD7944BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14B 2.5MSPS PULSR 20LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.5M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
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AD7944
Rev. A | Page 22 of 28
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7944 is connected
to an SPI-compatible digital host with an interrupt input and
when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This independence is particularly important in applica-
tions where low jitter on CNV is desired. This mode is available
only in normal conversion mode (TURBO low). The connection
diagram is shown in Figure 32, and the corresponding timing is
given in Figure 33.
With SDI high, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers, but
SDI must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high imped-
ance to low impedance. With a pull-up on the SDO line, this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7944 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an accept-
able hold time. After the optional 15th SCK falling edge or when
SDI goes high (whichever occurs first), SDO returns to high
impedance.
AD7944
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
IRQ
VIO
47k
CS1
TURBO
04658-
015
Figure 32. CS Mode, 4-Wire with Busy Indicator Connection Diagram
(I/O QUIET
TIME)
SDO
D13
D12
D1
D0
tDIS
tQUIET
SCK
1
2
3
13
14
15
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
TURBO = 0
04658-
016
Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
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