參數(shù)資料
型號: AD7944BCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 11/28頁
文件大?。?/td> 0K
描述: IC ADC 14B 2.5MSPS PULSR 20LFCSP
標準包裝: 1,500
系列: PulSAR®
位數(shù): 14
采樣率(每秒): 2.5M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 33mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤,CSP
供應商設備封裝: 20-LFCSP-VQ
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個偽差分,單極
AD7944
Rev. A | Page 19 of 28
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7944 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 26, and the corresponding timing is given in
With SDI tied to VIO, a rising edge on CNV initiates a con-
version, selects CS mode, and forces SDO to high impedance.
When a conversion is initiated, it continues until completion,
irrespective of the state of CNV. This can be useful, for example,
to bring CNV low to select other SPI devices, such as analog
multiplexers; however, CNV must be returned high before the
minimum conversion time elapses and then held high for the
maximum possible conversion time to avoid the generation of
the busy signal indicator.
When the conversion is complete, the AD7944 enters the
acquisition phase and, if the part is in normal mode (TURBO
low), powers down. When CNV goes low, the MSB is output
onto SDO. The remaining data bits are clocked by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can be used to capture the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
that it has an acceptable hold time. After the 14th SCK falling
edge or when CNV goes high (whichever occurs first), SDO
returns to high impedance.
AD7944
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
VIO
04658-
009
Figure 26. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
ACQUISITION (n)
ACQUISITION
(n + 1)
ACQUISITION
(n – 1)
1
2
BEGIN DATA (n – 1)
CONVERSION (n)
END DATA (n – 1)
SCK
CNV
SDO
12
13
CONVERSION (n – 1)
END DATA (n – 2)
tCONV
tDATA
0
(I/O QUIET
TIME)
(I/O QUIET
TIME)
14
12
13
14
1
13
12
11
2
0
1
2
SDI = 1
>
tCONV
(I/O QUIET
TIME)
tCYC
tACQ
tCNVH
tQUIET
tSCK
tDIS
tEN
tDSDO
tHSDO
tDATA
tCONV
04658-
010
Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
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