參數(shù)資料
型號(hào)： AD7938BSUZ-6
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 8CHAN 32TQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極；4 個(gè)偽差分，單極；7 偽差分，單極
配用： EVAL-AD7938CBZ-ND - EVAL BOARD FOR AD7938
Data Sheet
AD7938-6
Rev. C | Page 25 of 32
Writing Data to the AD7938-6
With W/B tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7938-6. The DB8/HBEN pin assumes its DB8 function. Data
written to the AD7938-6 should be provided on the DB0 to
DB11 inputs with DB0 being the LSB of the data-word. With
W/B tied logic low, the AD7938-6 requires two write operations
to transfer a full 12-bit word. DB8/HBEN assumes its HBEN
function. Data written to the AD7938-6 should be provided on
the DB0 to DB7 inputs. HBEN determines whether the byte
written is high byte or low byte data. The low byte of the data-
word should be written first with DB0 being the LSB of the full
data-word. For the high byte write, HBEN should be high and
the data on the DB0 input should be Bit 8 of the 12-bit word. In
both word mode and byte mode, a single write operation to the
shadow register is always sufficient since it is only 8-bits wide.
Figure 37 shows the write cycle timing diagram of the AD7938-6
in word mode. When operating in word mode, the HBEN input
does not exist and only one write operation is required to write
the word of data to the device. Data should be provided on DB0
to DB11. When operating in byte mode, the two write cycles
shown in Figure 38 are required to write the full data-word to
the AD7938-6. In Figure 38, the first write transfers the lower
eight bits of the data-word from DB0 to DB7, and the second
write transfers the upper four bits of the data-word. When
writing to the AD7938-6, the top four bits in the high byte must
be 0s.
The data is latched into the device on the rising edge of WR.
The data needs to be set up a time, t7, before the WR rising edge
and held for a time, t8, after the WR rising edge. The CS and
WR signals are gated internally. CS and WR can be tied
together as the timing specifications for t4 and t5 are 0 ns
minimum (assuming CS and RD have not already been tied
together).
t8
t5
t7
t6
t4
DATA
DB0 TO DB11
WR
CS
04
75
1-
00
2
Figure 37. AD7938-6 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/B = 1)
t5
t4
t7
t18
t19
t8
t6
t17
LOW BYTE
HIGH BYTE
DB0 TO DB11
HBEN/DB8
WR
CS
04
75
1-
0
03
Figure 38. AD7938-6 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/B = 0)
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