- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗1983 > AD7829BRW-1 (Analog Devices Inc)IC ADC 8BIT 8CH 2MSPS 28-SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD7829BRW-1 |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 3/20闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 8BIT 8CH 2MSPS 28-SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 27 |
| 浣嶆暩(sh霉)锛� | 8 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 2M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 36mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 28-SOIC W |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 8 鍊�(g猫)鍠锛屽柈妤� |
绗�1闋�(y猫)绗�2闋�(y猫)鐣�(d膩ng)鍓嶇3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)
AD7829-1
Rev. 0 | Page 11 of 20
A suggestion is to tie CONVST
ANALOG INPUT
to VDD or DGND through a
pull-up or pull-down resistor. A rising edge on the CONVST
pin causes the AD7829-1 to fully power up. For applications
where power consumption is of concern, the automatic power-
down at the end of a conversion should be used to improve
power performance (see the
The AD7829-1 has eight input channels. Each input channel has
an input span of 2.5 V or 2.0 V, depending on the supply voltage
(VDD). This input span is automatically set up by an on-chip
鈥淰DD detector鈥� circuit. A 5 V operation of the ADCs is detected
when VDD exceeds 4.1 V, and a 3 V operation is detected when
VDD falls below 3.8 V. This circuit also possesses a degree of
glitch rejection; for example, a glitch from 5.5 V to 2.7 V up to
60 ns wide does not trip the VDD detector.
Power vs. Throughput section).
If the AD7829-1 is operated outside normal VDD limits (for
example, a brown-out), it may take two conversions to reset the
part once the correct VDD has been established.
SUPPLY
4.5V TO 5.5V
10F
0.1F
VDD
VREF
VMID
VIN1
1.25V TO
3.75V INPUT
VIN2
VIN8
AGND
DB0 TO DB7
EOC
RD
CS
CONVST
A0
A1
A2
PARALLEL
INTERFACE
C/P
AD7829-1
DGND
2.5V
AD780
06
17
9-
00
8
The VMID pin is used to center this input span anywhere in the
range of AGND to VDD. If no input voltage is applied to VMID,
the default input range is AGND to 2.0 V (VDD = 3 V 卤 10%),
that is, centered about 1.0 V; or AGND to 2.5 V (VDD = 5 V 卤 10%),
that is, centered about 1.25 V. When using the default input range,
the VMID pin can be left unconnected; or, in some cases, it can be
decoupled to AGND with a 0.1 渭F capacitor.
If, however, an external VMID is applied, the analog input range
is from VMID 1.0 V to VMID + 1.0 V (VDD = 3 V 卤 10%), or from
VMID 1.25 V to VMID + 1.25 V (VDD = 5 V 卤 10%).
The range of values of VMID that can be applied depends on the
value of VDD. For VDD = 3 V 卤 10%, the range of values that can
be applied to VMID is from 1.0 V to VDD 1.0 V and is 1.25 V to
ranges of VMID and the input span for various values of VDD.
Figure 7. Typical Connection Diagram
Figure 9 illustrates the input signal range available with various
values of VMID.
ADC TRANSFER FUNCTION
The output coding of the AD7829-1 is straight binary. The
designed code transitions occur at successive integer LSB values
(that is, 1 LSB, 2 LSBs, and so on). The LSB size is equal to
VREF/256 (VDD = 5 V), or the LSB size is equal to (0.8 VREF)/256
(VDD = 3 V). The ideal transfer characteristic for the AD7829-1
is shown in
Table 5.
VMID
Internal
VMID Ext
Minimum
VMID Ext
Maximum
VDD
VIN Span
5.5
1.25
4.25
3.0 to 5.5
1.25
0 to 2.5
11111111
111...110
111...000
10000000
000...111
000...010
00000000
(VDD = 5V)
1LSB = VREF/256
(VDD = 3V)
1LSB = 0.8VREF/256
000...001
AD
C
CO
DE
1LSB
VMID
(VDD = 5V) VMID 鈥� 1.25V
(VDD = 3V) VMID 鈥� 1V
VMID + 1.25V 鈥� 1LSB
VMID + 1V 鈥� 1LSB
ANALOG INPUT VOLTAGE
0
61
79
-00
9
Figure 8. Transfer Characteristic
5.0
1.25
3.75
2.5 to 5.0
1.25
0 to 2.5
4.5
1.25
3.25
2.0 to 4.5
1.25
0 to 2.5
3.3
1.00
2.3
1.3 to 3.3
1.00
0 to 2.0
3.0
1.00
2.0
1.0 to 3.0
1.00
0 to 2.0
2.7
1.00
1.7
0.7 to 2.7
1.00
0 to 2.0
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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