
AD7829-1
Rev. 0 | Page 19 of 20
A0
A1
A2
CS
RD
DB7 TO DB0
A15 TO A3
CS
RD
DB0 TO DB7
A15 TO A3
A2 TO A0
ADC I/O ADDRESS
MUX ADDRESS
A/D RESULT
MUX ADDRESS
(CHANNEL SELECTION A0 TO A2)
LATCHED
MICROPROCESSOR READ CYCLE
ADDRESS
DECODE
SYST
EM
B
U
S
06
17
9-
02
8
AD7829-11
Figure 27. AD7829-1 Simplified Microinterfacing Scheme