參數(shù)資料
型號: AD7839ASZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 1/12頁
文件大?。?/td> 0K
描述: IC DAC 13BIT OCT VOLT OUT 44MQFP
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 800
設置時間: 30µs
位數(shù): 13
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 8
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 303mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-QFP
供應商設備封裝: 44-MQFP(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 8 電壓,單極;8 電壓,雙極
采樣率(每秒): 33k
配用: EVAL-AD7839EBZ-ND - BOARD EVAL FOR AD7839
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD7839
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
Octal 13-Bit, Parallel Input,
Voltage-Output DAC
FUNCTIONAL BLOCK DIAGRAM
DAC
REG
A
INPUT
REG
A
13
DAC E
AD7839
DB12
DB0
WR
CS
A0
A1
A2
LDAC
RR
R
13
DAC
REG
B
INPUT
REG
B
13
DAC
REG
C
INPUT
REG
C
13
DAC
REG
D
INPUT
REG
D
13
DAC
REG
E
INPUT
REG
E
13
DAC
REG
F
INPUT
REG
F
13
DAC
REG
G
INPUT
REG
G
13
DAC
REG
H
INPUT
REG
H
13
DAC D
DAC C
DAC F
DAC B
DAC A
DAC G
DAC H
VCC
VSS
VDD
VREF(+)
AB
VREF(–)
AB
DUTGND
CD
DUTGND
AB
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
DUTGND
GH
DUTGND
EF
VREF(–)
CDEF
VREF(+)
CDEF
VREF(–)
GH
VREF(+)
GH
GND
CLR
ADDRESS
DECODE
FEATURES
Eight 13-Bit DACs in One Package
Voltage Outputs
Offset Adjust for Each DAC Pair
Reference Range of
5 V
Maximum Output Voltage Range of
10 V
Clear Function to User-Defined Voltage
44-Lead MQFP Package
APPLICATIONS
Automatic Test Equipment
Process Control
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7839 contains eight 13-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of
±10 V
from reference voltages of
±5 V.
The AD7839 accepts 13-bit parallel loaded data from the exter-
nal bus into one of the input registers under the control of the
WR, CS and DAC channel address pins, A0–A2.
The DAC outputs are updated on reception of new data into
the DAC registers. All the outputs may be updated simulta-
neously by taking the
LDAC input low.
Each DAC output is buffered with a gain-of-two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.
The AD7839 is available in a 44-lead MQFP package.
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