參數(shù)資料
型號(hào)： AD7792BRU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/33頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 3CH LP 16-TSSOP
標(biāo)準(zhǔn)包裝： 96
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸入數(shù)目和類型： 3 個(gè)差分，單極；3 個(gè)差分，雙極
配用： EVAL-AD7792EBZ-ND - BOARD EVALUATION FOR AD7792
AD7792/AD7793
Rev. B | Page 15 of 32
STATUS REGISTER
RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7792)/0x88 (AD7793)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 13 outlines the bit designations for the status
register. SR0 through SR7 indicate the bit locations, and SR denotes that the bits are in the status register. SR7 denotes the first bit of the
data stream. The number in parentheses indicates the power-on/reset default status of that bit.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY(1)
ERR(0)
0(0)
0/1
CH2(0)
CH1(0)
CH0(0)
Table 13. Status Register Bit Designations
Bit Location
Bit Name
Description
SR7
RDY
Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically
after the ADC data register has been read or a period of time before the data register is updated with a new
conversion result to indicate to the user not to read the conversion data. It is also set when the part is
placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin can
be used as an alternative to the status register for monitoring the ADC for conversion data.
SR6
ERR
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to
the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange and underrange.
Cleared by a write operation to start a conversion.
SR5 to SR4
0
These bits are automatically cleared.
SR3
0/1
This bit is automatically cleared on the AD7792 and is automatically set on the AD7793.
SR2 to SR0
CH2 to CH0
These bits indicate which channel is being converted by the ADC.
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the
operating mode, update rate, and clock source. Table 14 outlines the bit designations for the mode register. MR0 through MR15 indicate
the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in parentheses
indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit.
MR15
MR14
MR13
MR12
MR11
MR10
MR9
MR8
MD2(0)
MD1(0)
MD0(0)
0(0)
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
CLK1(0)
CLK0(0)
0(0)
FS3(1)
FS2(0)
FS1(1)
FS0(0)
Table 14. Mode Register Bit Designations
Bit Location
Bit Name
Description
MR15 to
MR13
MD2 to
MD0
Mode Select Bits. These bits select the operational mode of the AD7792/AD7793 (see Table 15).
MR12 to MR8
0
These bits must be programmed with a Logic 0 for correct operation.
MR7 to MR6
CLK1 to
CLK0
These bits are used to select the clock source for the AD7792/AD7793. Either an on-chip 64 kHz clock can be
used, or an external clock can be used. The ability to override using an external clock allows several
AD7792/AD7793 devices to be synchronized. In addition, 50 Hz/60 Hz is improved when an accurate external
clock drives the AD7792/AD7793.
CLK1
CLK0
ADC Clock Source
0
Internal 64 kHz Clock. Internal clock is not available at the CLK pin.
0
1
Internal 64 kHz Clock. This clock is made available at the CLK pin.
1
0
External 64 kHz Clock Used. An external clock gives better 50 Hz/60 Hz rejection. See
specifications for external clock.
1
External Clock Used. The external clock is divided by 2 within the AD7792/AD7793.
MR5 to MR4
0
These bits must be programmed with a Logic 0 for correct operation.
MR3 to MR0
FS3 to FS0
Filter Update Rate Select Bits (see Table 16).
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