- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373915 > AD7723 (Analog Devices, Inc.) 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC PDF資料下載
參數(shù)資料
| 型號(hào)： | AD7723 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| 中文描述： | 16位，120 MSPS的的CMOS，Σ-Δ模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 21/23頁 |
| 文件大?。?/td> | 435K |
| 代理商： | AD7723 |
AD7723
–21–
REV. 0
SERIAL INTERFACE TO DSPS
In serial mode, the AD7723 can be directly interfaced to several
industry standard digital signal processors. In all cases, the
AD7723 operates as the master with the DSP operating as the
slave. The AD7723 provides its own serial clock (SCO) to
transmit the digital word on the SDO pin to the DSP. The
AD7723 also generates the frame synchronization signal
that
synchronizes the transfer of the 16-bit word from the AD7723
to the DSP. Depending on the serial mode used, SCO will have
a frequency equal to CLKIN or equal to CLKIN/2. When SCO
equals 19.2 MHz, the AD7723 can be interfaced to Analog
Devices’ ADSP-2106x SHARC DSP. With a 19.2 MHz master
clock and SCO equal to CLKIN/2, the AD7723 can be inter-
faced with the ADSP-21xx family of DSPs, the DSP56002
and the TMS320C5x-57. When the
AD7723 is used in the
HALF_PWR mode, i.e., CLKIN is less than 10 MHz, then the
AD7723 can be used with DSPs such as the TMS320C20/C25
and the DSP56000/1.
AD7723-to-ADSP-21xx Interface
Figure 41 shows the interface between the ADSP-21xx and the
AD7723. The AD7723 is operated in Mode 2 so that SCO =
CLKIN/2. For the ADSP-21xx, the bits in the serial port con-
trol register should be set up as RFSR = 1 (a frame sync is
needed for each transfer), SLEN = 15 (16-bit word lengths),
RFSW = 0 (normal framing mode for receive operations),
INVRFS = 0 (active high RFS), IRFS = 0 (external RFS) and
ISCLK = 0 (external serial clock).
DR
RFS
SCLK
ADSP-21xx
SDO
FSO
SCO
AD7723
Figure 41. AD7723-to-ADSP-21xx Interface
AD7723-to-SHARC Interface
The interface between the AD7723 and the ADSP-2106x
SHARC DSP is the same as shown in Figure 41 but, the DSP is
configured as follows: SLEN = 15 (16-bit word transfers),
SENDN = 0 (the MSB of the 16-bit word will be received by
the DSP first), ICLK = 0 (an external serial clock will be used),
RFSR = 0 (a frame sync is required for every word transfer),
IRFS = 0 (the receive frame sync signal is external), CKRE = 0
CLKIN
FSI
SCO
FSO (MASTER)
FSI (SLAVE)
DOE (MASTER & SLAVE)
SDO (MASTER)
SDO (SLAVE)
D1
D0
D15
D14
D15
D14
D1
D0
t
11
t
12
t
13
t
9
t
15
t
16
t
16
t
15
Figure 40. Serial Mode 1 Timing for Two-Channel Multiplexed Operation
(the receive data will be latched into the DSP on the falling
clock edge), LAFS = 0 (the DSP begins reading the 16-bit word
after the DSP has identified the frame sync signal rather than
the DSP reading the word at the same instant as the frame sync
signal has been identified), LRFS = 0 (RFS is active high).
The AD7723 can be used in Modes 1, 2 or 3 when interfaced to
the ADSP-2106x SHARC DSP.
AD7723-to-DSP56002 Interface
Figure 42 shows the AD7723-to-DSP56002 interface. To inter-
face the AD7723 to the DSP56002, the ADC is operated in
Mode 2 when the ADC is operated with a 19.2 MHz clock. The
DSP56002 is configured as follows: SYN = 1 (synchronous
mode), SCD1 = 0 (RFS is an input), GCK = 0 (a continuous
serial clock is used), SCKD = 0 (the serial clock is external),
WL1 = l, WL0 = 0 (transfers will be 16 bits wide), FSL1 = 0,
FSL0 = 1 (the frame sync will be active at the beginning of each
transfer). Alternatively, the DSP56002 can be operated in asyn-
chronous mode (SYN = 0).
In this mode, the serial clock for the receive section is input to
the SCO pin. This is accomplished by setting bit SCDO to 0
(external Rx clock).
SDR
SC1
SCK
DSP56002
SDO
FSO
SCO
AD7723
Figure 42. AD7723-to-DSP56002 Interface
AD7723-to-TMS320C5x Interface
Figure 43 shows the AD7723-to-TMS320C5x interface. For the
TMS320C5x, FSR and CLKR are automatically configured as
inputs. The serial port is configured as follows: FO = 0 (16-bit
word transfers), FSM = 1 (a frame sync occurs for each transfer).
DR
FSR
CLKR
TMS320C5x
SDO
FSO
SCO
AD7723
Figure 43. AD7723-to-TMS320C5x Interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7723BS | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7724AST | Dual CMOS Modulators |
| AD7724 | Dual CMOS Modulators |
| AD7725 | 16-Bit 900 kSPS ADC with a Programmable Postprocessor |
| AD7725BS | 16-Bit 900 kSPS ADC with a Programmable Postprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7723BS | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 19.2Msps 16-bit Parallel/Serial 44-Pin MQFP 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD7723BS-REEL | 制造商:Analog Devices 功能描述:Single ADC Delta-Sigma 19.2Msps 16-bit Parallel/Serial 44-Pin MQFP T/R |
| AD7723BSZ | 功能描述:IC ADC 16BIT SIGMA-DELTA 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7723BSZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7723BSZ-REEL | 功能描述:IC ADC 16BIT SIGMA-DELTA 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。