參數(shù)資料
型號(hào)： AD7723
廠商： Analog Devices, Inc.
英文描述： 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC
中文描述： 16位，120 MSPS的的CMOS，Σ-Δ模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 19/23頁(yè)
文件大小： 435K
代理商： AD7723
AD7723
–19–
REV. 0
Clock Generation
The AD7723 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. The connection diagram for use with a crystal is shown in
Figure 37. Consult the manufacturer’s recommendation for the
load capacitors. To enable the oscillator circuit on board the
AD7723, XTAL_OFF should be tied low.
1M
V
XTAL
CLKIN
AD7723
Figure 37. Crystal Oscillator Connection
When an external clock source is being used, the internal oscil-
lator circuit can be disabled by tying XTAL_OFF high. A low
phase noise clock should be used to generate the ADC sampling
clock because sampling clock jitter effectively modulates the
input signal and raises the noise floor. The sampling clock gen-
erator should be isolated from noisy digital circuits, grounded
and heavily decoupled to the analog ground plane.
The sampling clock generator should be referenced to the ana-
log ground in a split ground system. However, this is not always
possible because of system constraints. In many applications,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital
ground plane. If the clock signal is passed between its origin on
a digital ground plane to the AD7723 on the analog ground
plane, the ground noise between the two planes adds directly to
the clock and will produce excess jitter. The jitter can cause
degradation in the signal-to-noise ratio and also produce un-
wanted harmonics. This can be remedied somewhat by trans-
mitting the sampling signal as a differential one, using either a
small RF transformer or a high speed differential driver and a
receiver such as PECL. In either case, the original master sys-
tem clock should be generated from a low phase noise crystal
oscillator.
SYSTEM SYNCHRONIZATION
The SYNC input provides a synchronization function for use in
parallel or serial mode. SYNC allows the user to begin gathering
samples of the analog input from a known point in time. This
allows a system using multiple AD7723s, operated from a com-
mon master clock, to be synchronized so that each ADC simul-
taneously updates its output register.
In a system using multiple AD7723s, a common signal to their
sync inputs will synchronize their operation. On the rising edge
of SYNC, the digital filter sequencer is reset to zero. The filter
is held in a reset state until a rising edge on CLKIN senses
SYNC low. A SYNC pulse, one CLKIN cycle long, can be
applied synchronous to the falling edge of CLKIN. This way, on
the next rising edge of CLKIN, SYNC is sensed low, the filter is
taken out of its reset state and multiple parts begin to gather
input samples.
Following a SYNC, the modulator and filter need time to settle
before data can be read from the AD7723.
DRDY
goes high
following a synchronization and it remains high until valid data
is available at the interface.
DATA INTERFACING
The AD7723 offers a choice of serial or parallel data interface
options to meet the requirements of a variety of system configu-
rations. In parallel mode, multiple AD7723s can easily be con-
figured to share a common data bus. Serial mode is ideal when
it is required to minimize the number of data interface lines
connected to a host processor. In either case, careful attention
to the system configuration is required to realize the high dy-
namic range available with the AD7723. Consult the recom-
mendation in the Layout and Grounding section. The following
recommendations for parallel interfacing also apply for the sys-
tem design when using the serial mode.
Parallel Interface
When using the AD7723, place a buffer/latch adjacent to the
converter to isolate the converter’s data lines from any noise
which may be on the data bus. Even though the AD7723 has
three state outputs, use of an isolation latch represents good
design practice.
Figure 38 shows how the parallel interface of the AD7723 can
be configured to interface with the system data bus of a micro-
processor or a microcontroller such as the MC68HC16 or
8XC251. With
CS
and
RD
tied permanently low, the data out-
put bits are always active. When
DRDY
goes high for two clock
cycles, the rising edge of
DRDY
is used to latch the conversion
data before a new conversion result is loaded into the output
data register. The falling edge of
DRDY
then sends an appropri-
ate interrupt signal for interface control. Alternatively, if buffers
are used instead of latches, the falling edge of
DRDY
provides
the necessary interrupt when a new output word is available
from the AD7723.
DSP
ADDR
DECODE
DB0–15
DRDY
CS
RD
16
16
OE
D0–15
RD
INTERRUPT
ADDR
AD7723
74XX16374
Figure 38. Parallel Interface Connection
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