參數(shù)資料
型號: AD7723
廠商: Analog Devices, Inc.
英文描述: 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC
中文描述: 16位,120 MSPS的的CMOS,Σ-Δ模數(shù)轉(zhuǎn)換器
文件頁數(shù): 10/23頁
文件大?。?/td> 435K
代理商: AD7723
AD7723
–10–
REV. 0
PARALLEL MODE PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No.
Description
DV
DD
/
CS
CFMT/
RD
30
4
Chip Select Logic Input.
Read Logic Input. Used in conjunction with
CS
to read data from the parallel bus. The output data
bus is enabled when the rising edge of CLKIN senses a logic low level on
RD
if
CS
is also low. When
RD
is sensed high, the output data bits, DB15–DB0 will be high impedance.
Data Ready Logic Output. A falling edge indicates a new output word is available to be read from
the output data register.
DRDY
will return high upon completion of a read operation. If a read operation
does not occur between output updates,
DRDY
will pulse high for two CLKIN cycles before the next
output update.
DRDY
also indicates when conversion results are available after a SYNC sequence.
Data Output Bit, (MSB)
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit.
Data Output Bit, (LSB).
DGND/
DRDY
5
DGND/DB15
DGND/DB14
SCR/DB13
SLDR/DB12
SLP/DB11
TSI/DB10
FSO/DB9
SDO/DB8
SCO/DB7
FSI/DB6
SFMT/DB5
DOE/DB4
DGND/DB3
DGND/DB2
DGND/DB1
DGND/DB0
31
32
33
34
35
36
37
38
40
41
42
43
44
1
2
3
相關PDF資料
PDF描述
AD7723BS 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC
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AD7725 16-Bit 900 kSPS ADC with a Programmable Postprocessor
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