AVDD = DVDD " />
參數(shù)資料
型號(hào)： AD7707BR
廠商： Analog Devices Inc
文件頁數(shù)： 51/52頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 3CH 20-SOIC
標(biāo)準(zhǔn)包裝： 37
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)單端，雙極；2 個(gè)偽差分，單極；2 個(gè)偽差分，雙極
AD7707
Rev. B | Page 8 of 52
TIMING CHARACTERISTICS
AVDD = DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; input logic = 0, Logic 1 = DVDD, unless otherwise noted.
Table 4.
Parameter1, 2
Limit at TMIN, TMAX
(B Version)
Unit
Conditions/Comments
fCLKIN3, 4
400
kHz min
Master clock frequency: crystal oscillator or externally supplied for specified performance
5
MHz max
tCLKIN LO
0.4 × tCLKIN
ns min
Master clock input low time, tCLKIN = 1/fCLKIN
tCLKIN HI
0.4 × tCLKIN
ns min
Master clock input high time
t1
500 × tCLKIN
ns nom
DRDY high time
t2
100
ns min
RESET pulse width
Read Operation
t3
0
ns min
DRDY to CS setup time
t4
120
ns min
CS falling edge to SCLK rising edge setup time
0
ns min
SCLK falling edge to data valid delay
80
ns max
DVDD = 5 V
100
ns max
DVDD = 3.0 V
t6
100
ns min
SCLK high pulse width
t7
100
ns min
SCLK low pulse width
t8
0
ns min
CS rising edge to SCLK rising edge hold time
10
ns min
Bus relinquish time after SCLK rising edge
60
ns max
DVDD = 5 V
100
ns max
DVDD = 3.0 V
t10
100
ns max
SCLK falling edge to DRDY high7
Write Operation
t11
120
ns min
CS falling edge to SCLK rising edge setup time
t12
30
ns min
Data valid to SCLK rising edge setup time
t13
20
ns min
Data valid to SCLK rising edge hold time
t14
100
ns min
SCLK high pulse width
t15
100
ns min
SCLK low pulse width
t16
0
ns min
CS rising edge to SCLK rising edge hold time
1 Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
3 fCLKIN duty cycle range is 45% to 55%. fCLKIN must be supplied whenever the AD7707 is not in standby mode. If no clock is present in this case, the device can draw
higher current than specified and possibly become uncalibrated.
4 The AD7707 is production tested with fCLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz.
5 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
7
DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care should
be taken that subsequent reads do not occur close to the next output update.
TO OUTPUT
PIN
50pF
ISINK (800A AT VDD = 5V
100A AT VDD = 3V)
1.6V
ISOURCE (200A AT VDD = 5V
100A AT VDD = 3V)
08
69
1-
00
2
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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AD7707BR-REEL 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 20-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 20SOIC W - Tape and Reel
AD7707BR-REEL7 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 20-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 20SOIC W - Tape and Reel
AD7707BRU 功能描述:IC ADC 16BIT 3CH 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
AD7707BRU-REEL 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 500sps 16-bit Serial 20-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.5KSPS 16BIT SERL 20TSSOP - Tape and Reel
AD7707BRU-REEL7 功能描述:IC ADC 16BIT 3CH 20-TSSOP T/R RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極
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