B Version1 Unit Conditions/Comments MCLK IN Only
參數(shù)資料
型號(hào)： AD7707BR
廠商： Analog Devices Inc
文件頁數(shù)： 49/52頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 3CH 20-SOIC
標(biāo)準(zhǔn)包裝： 37
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)單端，單極；1 個(gè)單端，雙極；2 個(gè)偽差分，單極；2 個(gè)偽差分，雙極
AD7707
Rev. B | Page 6 of 52
Parameter
B Version1
Unit
Conditions/Comments
MCLK IN Only
DVDD = 5 V nominal
VINL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
3.5
V min
MCLK IN Only
DVDD = 3 V nominal
VINL, Input Low Voltage
0.4
V max
VINH, Input High Voltage
2.5
V min
LOGIC OUTPUTS (Including MCLK OUT)
VOL, Output Low Voltage
0.4
V max
ISINK = 800 μA except for MCLK OUT13; DVDD = 5 V
0.4
V max
ISINK = 100 μA except for MCLK OUT13; DVDD = 3 V
VOH, Output High Voltage
4
V min
ISOURCE = 200 μA except for MCLK OUT13; DVDD = 5 V
DVDD 0.6
V min
ISOURCE = 100 μA except for MCLK OUT13; DVDD = 3 V
Floating State Leakage Current
±10
μA max
Floating State Output Capacitance14
9
pF typ
Data Output Coding
Binary
Unipolar mode
Offset binary
Bipolar mode
SYSTEM CALIBRATION
Low Level Input Channels (AIN1 and AIN2)
Positive Full-Scale Calibration Limit15
(1.05 ×
VREF)/gain
V max
Gain is the selected PGA gain (1 to 128)
Negative Full-Scale Calibration Limit15
(1.05 ×
VREF)/gain
V max
Gain is the selected PGA gain (1 to 128)
Offset Calibration Limit16
(1.05 ×
VREF)/gain
V max
Gain is the selected PGA gain (1 to 128)
Input Span16
(0.8 × VREF)/gain
V min
Gain is the selected PGA gain (1 to 128)
(2.1 × VREF)/gain
V max
Gain is the selected PGA gain (1 to 128)
High Level Input Channels (AIN3)
Positive Full-Scale Calibration Limit15
(8.4 × VREF)/gain
V max
Gain is the selected PGA gain (1 to 128)
Negative Full-Scale Calibration Limit15
(8.4 ×
VREF)/gain
V max
Gain is the selected PGA gain (1 to 128)
Offset Calibration Limit16
(8.4 ×
VREF)/gain
V max
Gain is the selected PGA gain (1 to 128)
Input Span16
(6.4 × VREF)/gain
V min
Gain is the selected PGA gain (1 to 128)
(16.8 ×
VREF)/gain
V max
Gain is the selected PGA gain (1 to 128)
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage
2.7 to 3.3 or
4.75 to 5.25
V min to V max
For specified performance
DVDD Voltage
2.7 to 5.25
V min to V max
For specified performance
Power Supply Currents
AVDD Current
AVDD = 3 V or 5 V; gain = 1 to 4
0.27
mA max
Typically 0.22 mA; BUF = 0; fCLKIN = 1 MHz or 2.4576 MHz
0.6
mA max
Typically 0.45 mA; BUF = 1; fCLKIN = 1 MHz or 2.4576 MHz
AVDD = 3 V or 5 V; gain = 8 to 128
0.5
mA max
Typically 0.38 mA; BUF = 0; fCLK IN = 2.4576 MHz
1.1
mA max
Typically 0.81 mA; BUF = 1; fCLK IN = 2.4576 MHz
POWER REQUIREMENTS (Continued)
Digital inputs = 0 V or DVDD; external MCLK IN
0.080
mA max
Typically 0.06 mA; DVDD = 3 V; fCLK IN = 1 MHz
0.15
mA max
Typically 0.13 mA; DVDD = 5 V; fCLK IN = 1 MHz
0.18
mA max
Typically 0.15 mA; DVDD = 3 V; fCLK IN = 2.4576 MHz
0.35
mA max
Typically 0.3 mA; DVDD = 5 V; fCLK IN = 2.4576 MHz
Power Supply Rejection18, 19
dB typ
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