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參數(shù)資料
型號： AD7707BR
廠商： Analog Devices Inc
文件頁數(shù)： 50/52頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 3CH 20-SOIC
標(biāo)準(zhǔn)包裝： 37
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 管件
輸入數(shù)目和類型： 1 個單端，單極；1 個單端，雙極；2 個偽差分，單極；2 個偽差分，雙極
AD7707
Rev. B | Page 7 of 52
Parameter
B Version1
Unit
Conditions/Comments
Normal Mode Power Dissipation17
AVDD = DVDD = 3 V; digital inputs = 0 V or DVDD; external
MCLK IN excluding dissipation in the AIN3 attenuator
1.05
mW max
Typically 0.84 mW; BUF = 0; fCLKIN = 1 MHz, all gains
2.04
mW max
Typically 1.53 mW; BUF = 1; fCLK IN = 1 MHz; all gains
1.35
mW max
Typically 1.11 mW; BUF = 0; fCLK IN = 2.4576 MHz,
gain = 1 to 4
2.34
mW max
Typically 1.9 mW; BUF = 1; fCLK IN = 2.457 6 MHz;
gain = 1 to 4
Normal Mode Power Dissipation17
AVDD = DVDD = 5 V; digital inputs = 0 V or DVDD;
external MCLKIN
2.1
mW max
Typically 1.75 mW; BUF = 0; fCLKIN = 1 MHz; all gains
3.75
mW max
Typically 2.9 mW; BUF = 1; fCLKIN = 1 MHz; all gains
3.1
mW max
Typically 2.6 mW; BUF = 0; fCLK IN = 2.4576 MHz
4.75
mW max
Typically 3.75 mW; BUF = 1; fCLK IN = 2.4576 MHz
Standby (Power-Down) Current20
18
μA max
External MCLK IN = 0 V or DVDD; typically 9 μA;
AVDD = 5 V
8
μA max
External MCLK IN = 0 V or DVDD; typically 4 μA;
AVDD = 3 V
1 Temperature range as follows: B Version, 40°C to +85°C.
2 These numbers are established from characterization or design at initial product release.
3 A calibration is effectively a conversion so these errors are of the order of the conversion noise shown in Table 7 and Table 9 for the low level input channels AIN1 and
AIN2. This applies after calibration at the temperature of interest.
4 Recalibration at any temperature removes these drift errors.
5 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.
6 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.
7 Gain error does not include zero-scale errors. It is calculated as full-scale error—unipolar offset error for unipolar ranges and full-scale error—bipolar zero error for
bipolar ranges.
8 Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if
zero-scale calibrations were performed.
9 Error is removed following a system calibration.
10 This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AVDD + 30 mV or go more negative
than AGND 100 mV. Parts are functional with voltages down to AGND 200 mV, but with increased leakage at high temperature.
11 The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with
respect to the HCOM input on the high level input channel, AIN3. The absolute voltage on the low level analog inputs should not go more positive than AVDD +
100 mV, or go more negative than GND 100 mV for specified performance. Input voltages of AGND 200 mV can be accommodated, but with increased leakage at
high temperature.
12 VREF = REF IN(+) REF IN().
13 These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
14 Sample tested at +25°C to ensure compliance.
15 After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s.
16 These calibration and span limits apply provided that the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND
mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
17 When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation varies depending on the
crystal or resonator type (see the Clocking and Oscillator Circuit section).
18 Measured at dc and applies in the selected pass band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter
notches of 20 Hz or 60 Hz.
19 PSRR depends on both gain and AVDD. See Table 2 and Table 3.
20 If the external master clock continues to run in standby mode, the standby current increases to 150 μA typical at 5 V and 75 μA typical at 3 V. When using a crystal or
ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends
on the crystal or resonator type (see the Standby Mode section).
Table 2. Low Level Input Channels, AIN1 and AIN2
Gain
1
2
4
8 to 128
AVDD = 3 V
86
78
85
93
AVDD = 5 V
90
78
84
91
Table 3. High Level Input Channel, AIN3
Gain
1
2
4
8 to 128
AVDD = 3 V
68
60
67
75
AVDD = 5 V
72
60
66
73
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