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參數(shù)資料
| 型號： | AD7466BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187-AA, MSOP-8 |
| 文件頁數(shù)： | 28/28頁 |
| 文件大小： | 959K |
| 代理商： | AD7466BRM |
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AD7466/AD7467/AD7468
Rev. B | Page 9 of 28
TIMING SPECIFICATIONS
For all devices, VDD = 1.6 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input
signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.4 V.
Table 4.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK
3.4
MHz max
Mark/space ratio for the SCLK input is 40/60 to 60/40.
10
kHz min
1.6 V ≤ VDD ≤ 3 V; minimum fSCLK at which specifications are guaranteed.
20
kHz min
VDD = 3.3 V; minimum fSCLK at which specifications are guaranteed.
150
kHz min
VDD = 3.6 V; minimum fSCLK at which specifications are guaranteed.
tCONVERT
16 × tSCLK
AD7466.
12 × tSCLK
AD7467.
10 × tSCLK
AD7468.
Acquisition Time
Acquisition time/power-up time from power-down. See the Terminology
section. The acquisition time is the time required for the part to acquire a full-
scale step input value within ±1 LSB or a 30 kHz ac input value within ±0.5 LSB.
780
ns max
VDD = 1.6 V.
640
ns max
1.8 V ≤ VDD ≤ 3.6 V.
tQUIET
10
ns min
Minimum quiet time required between bus relinquish and the start of the next
conversion.
t1
10
ns min
Minimum CS pulse width.
t2
55
ns min
CS to SCLK setup time. If VDD = 1.6 V and fSCLK = 3.4 MHz, t2 has to be 192 ns
minimum in order to meet the maximum figure for the acquisition time.
t3
55
ns max
Delay from CS until SDATA is three-state disabled. Measured with the load
circuit in Figure 2 and defined as the time required for the output to cross the
VIH or VIL voltage.
t4
140
ns max
Data access time after SCLK falling edge. Measured with the load circuit in
voltage.
t5
0.4 tSCLK
ns min
SCLK low pulse width.
t6
0.4 tSCLK
ns min
SCLK high pulse width.
t7
10
ns min
SCLK to data valid hold time. Measured with the load circuit in Figure 2 and
defined as the time required for the output to cross the VIH or VIL voltage.
t8
60
ns max
SCLK falling edge to SDATA three-state. t8 is derived from the measured time
taken by the data outputs to change 0.5 V when loaded with the circuit in
Figure 2. The measured number is then extrapolated back to remove the effects
of charging or discharging the 50 pF capacitor. This means that the time, t8,
quoted in the timing characteristics is the true bus relinquish time of the part,
and is independent of the bus loading.
7
ns min
SCLK falling edge to SDATA three-state.
200
AI
OL
200
AI
OH
1.4V
TO OUTPUT
PIN
CL
50pF
02643-002
Figure 2. Load Circuit for Digital Output Timing Specifications
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| AD7466BRMZ | 功能描述:IC ADC 12BIT 1.6V LP 8-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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