參數(shù)資料
型號: AD7466BRM
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
中文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: MO-187-AA, MSOP-8
文件頁數(shù): 17/28頁
文件大?。?/td> 959K
代理商: AD7466BRM
AD7466/AD7467/AD7468
Rev. B | Page 24 of 28
For example, the ADSP-2181 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation
results in nonequidistant sampling as the transmit instruction is
occurring on an SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
AD7466/AD7467/AD7468 to DSP563xx Interface
The connection diagram in Figure 35 shows how the AD7466/
AD7467/AD7468 can be connected to the synchronous serial
interface (SSI) of the DSP563xx family of DSPs from Motorola.
The SSI is operated in synchronous mode and normal mode
(SYN = 1 and MOD = 0 in Control Register B, CRB) with an
internally generated word frame sync for both Tx and Rx
(Bits FSL1 = 0 and FSL0 = 0 in the CRB register). Set the
word length in Control Register A (CRA) to 16 by setting Bits
WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7466. The word
length for the AD7468 can be set to 12 bits (WL2 = 0, WL1 = 0,
and WL0 = 1). This DSP does not offer the option for a 14-bit
word length, so the AD7467 word length is set up to 16 bits like
the AD7466 word length. In this case, the user should keep in
mind that the last two bits are invalid data because the SDATA
goes back into three-state on the 14th SCLK falling edge.
The frame sync polarity bit (FSP) in the CRB register can be set
to 1, which means the frame goes low and a conversion starts.
Likewise, by means of Bits SCD2, SCKD, and SHFD in the CRB
register, it is established that Pins SC2 (the frame sync signal)
and SCK in the serial port are configured as outputs, and the
most significant bit (MSB) is shifted first. To summarize
MOD = 0
SYN = 1
WL2, WL1, WL0 depend on the word length
FSL1 = 0, FSL0 = 0
FSP = 1, negative frame sync
SCD2 = 1
SCKD = 1
SHFD = 0
For signal processing applications, it is imperative that the
frame synchronization signal from the DSP563xx provides
equidistant sampling.
AD7466/
AD7467/
AD74681
SCLK
1ADDITIONAL PINS OMITTED FOR CLARITY.
SDATA
ADSP-218x1
SCLK
DR
RFS
TFS
02643-034
CS
AD7466/
AD7467/
AD74681
1ADDITIONAL PINS OMITTED FOR CLARITY.
DSP563xx1
SDATA
SRD
SCLK
SCK
SC2
02643-035
CS
Figure 34. Interfacing to the ADSP-218x
Figure 35. Interfacing to the DSP563xx
相關PDF資料
PDF描述
AD7466BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7467BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7468BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7466 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
AD7467 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
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