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參數(shù)資料
| 型號： | AD7466BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187-AA, MSOP-8 |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 959K |
| 代理商： | AD7466BRM |
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AD7466/AD7467/AD7468
Rev. B | Page 19 of 28
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades.
Figure 13 shows a graph of THD vs. analog input signal
frequency for different source impedances when using a supply
voltage of 2.7 V and sampling at a rate of 100 kSPS.
DIGITAL INPUTS
The digital inputs applied to the AD7466/AD7467/AD7468
are not limited by the maximum ratings that limit the analog
inputs. Instead, the digital inputs applied can go to 7 V and are
not restricted by the VDD + 0.3 V limit as on the analog input.
For example, if the AD7466/AD7467/AD7468 are operated with
a VDD of 3 V, 5 V logic levels could be used on the digital inputs.
However, the data output on SDATA still has 3 V logic levels
when VDD = 3 V. Another advantage of SCLK and CS not
being restricted by the VDD + 0.3 V limit is that power supply
sequencing issues are avoided. If CS or SCLK is applied before
VDD, there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V is applied prior to VDD.
NORMAL MODE
The AD7466/AD7467/AD7468 automatically enter power-
down at the end of each conversion. This mode of operation is
designed to provide flexible power management options and to
optimize the power dissipation/throughput rate ratio for low
power application requirements. Figure 25 shows the general
operation of the AD7466/AD7467/AD7468. On the CS falling
edge, the part begins to power up and the track-and-hold, which
was in hold while the part was in power-down, goes into track
mode. The conversion is also initiated at this point. On the third
SCLK falling edge after the CS falling edge, the track-and-hold
returns to hold mode.
For the AD7466, 16 serial clock cycles are required to complete
the conversion and access the complete conversion result. The
AD7466 automatically enters power-down mode on the 16th
SCLK falling edge.
For the AD7467, 14 serial clock cycles are required to complete
the conversion and access the complete conversion result. The
AD7467 automatically enters power-down mode on the 14th
SCLK falling edge.
For the AD7468, 12 serial clock cycles are required to complete
the conversion and access the complete conversion result.
The AD7468 automatically enters power-down mode on the
12th SCLK falling edge.
The AD7466 also enters power-down mode if CS is brought
high any time before the 16th SCLK falling edge. The conver-
sion that was initiated by the CS falling edge terminates and
SDATA goes back into three-state. This also applies for the
AD7467 and AD7468; if CS is brought high before the conver-
sion is complete (the 14th SCLK falling edge for the AD7467,
and the 12th SCLK falling edge for the AD7468), the part enters
power-down, the conversion terminates, and SDATA goes back
into three-state.
Although CS can idle high or low between conversions,
bringing CS high once the conversion is complete is recom-
mended to save power.
When supplies are first applied to the devices, a dummy conver-
sion should be performed to ensure that the parts are in power-
down mode, the track-and-hold is in hold mode, and SDATA is
in three-state.
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
tQUIET, has elapsed, by bringing CS low again.
THE PART BEGINS
TO POWER UP
AD7468 ENTERS POWER-DOWN
AD7467 ENTERS POWER-DOWN
AD7466 ENTERS POWER-DOWN
VALID DATA
SCLK
SDATA
12
3
12
14
16
THE PART IS POWERED UP
AND VIN FULLY ACQUIRED
CS
02643-025
Figure 25. Normal Mode Operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7466BRT | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7467BRT | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7468BRT | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7466 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| AD7467 | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
相關(guān)代理商/技術(shù)參數(shù) |
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| AD7466BRM-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 8-Pin MSOP T/R |
| AD7466BRM-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 8-Pin MSOP T/R |
| AD7466BRMZ | 功能描述:IC ADC 12BIT 1.6V LP 8-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7466BRMZ-REEL | 功能描述:IC ADC 12BIT 1.6V LP 8-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
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