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參數(shù)資料
| 型號(hào)： | AD7466BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187-AA, MSOP-8 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 959K |
| 代理商： | AD7466BRM |
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AD7466/AD7467/AD7468
Rev. B | Page 5 of 28
AD7467 SPECIFICATIONS
VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted.
The temperature range for the B version is 40°C to +85°C.
Table 2.
Parameter
B Version
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Maximum/minimum specifications apply as typical figures
when VDD = 1.6 V, fIN = 30 kHz sine wave.
Signal-to-Noise and Distortion (SINAD)
61
dB min
See the Terminology section.
Total Harmonic Distortion (THD)
72
dB max
See the Terminology section.
Peak Harmonic or Spurious Noise (SFDR)
74
dB max
See the Terminology section.
Intermodulation Distortion (IMD)
fa = 29.1 kHz, fb = 29.9 kHz; see the Terminology section.
Second-Order Terms
83
dB typ
Third-Order Terms
83
dB typ
Aperture Delay
10
ns typ
Aperture Jitter
40
ps typ
Full-Power Bandwidth
3.2
MHz typ
@ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V.
1.9
MHz typ
@ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V.
750
kHz typ
@ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V.
450
kHz typ
@ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V.
DC ACCURACY
Maximum specifications apply as typical figures when
VDD = 1.6 V.
Resolution
10
Bits
Integral Nonlinearity
±0.5
LSB max
See the Terminology section.
Differential Nonlinearity
±0.5
LSB max
Guaranteed no missed codes to 10 bits;
see the Terminology section.
Offset Error
±0.2
LSB max
See the Terminology section.
Gain Error
±0.2
LSB max
See the Terminology section.
Total Unadjusted Error (TUE)
±1
LSB max
See the Terminology section.
ANALOG INPUT
Input Voltage Ranges
0 to VDD
V
DC Leakage Current
±1
A max
Input Capacitance
20
pF typ
LOGIC INPUTS
Input High Voltage, VINH
0.7 × VDD
V min
1.6 V ≤ VDD < 2.7 V.
2
V min
2.7 V ≤ VDD ≤ 3.6 V.
Input Low Voltage, VINL
0.2 × VDD
V max
1.6 V ≤ VDD < 1.8 V.
0.3 × VDD
V max
1.8 V ≤V DD < 2.7 V.
0.8
V max
2.7 V ≤ VDD ≤ 3.6 V.
Input Current, IIN, SCLK Pin
±1
A max
Typically 20 nA, VIN = 0 V or VDD.
Input Current, IIN, CS Pin
±1
A typ
Input Capacitance, CIN
10
pF max
Sample tested at 25°C to ensure compliance.
LOGIC OUTPUTS
Output High Voltage, VOH
VDD 0.2
V min
ISOURCE = 200 A, VDD = 1.6 V to 3.6 V.
Output Low Voltage, VOL
0.2
V max
ISINK = 200 A.
Floating-State Leakage Current
±1
A max
Floating-State Output Capacitance
10
pF max
Sample tested at 25°C to ensure compliance.
Output Coding
Straight (natural) binary
CONVERSION RATE
Conversion Time
3.52
s max
12 SCLK cycles with SCLK at 3.4 MHz.
Throughput Rate
275
kSPS max
See the Serial Interface section.
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