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| 型號： | AD7452BRT-R2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 555KSPS SOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 555k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 剪切帶 (CT) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
| 其它名稱： | AD7452BRT-R2CT |
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AD7452
Rev. B | Page 23 of 28
AD7452*
ADSP-21xx*
SCLK
DR
RFS
TFS
SCLK
SDATA
CS
03154-A
-040
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 40. Interfacing to the ADSP-21xx
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in
the SCLKDIV register. When the instruction to transmit with
TFS is given (i.e., AX0 = TX0), the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
again before the transmission starts. If the timer and SCLK
values are chosen such that the instruction to transmit occurs
on or near the rising edge of SCLK, the data may be transmitted
or it may wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and
subsequently between transmit instructions. This situation
results in nonequidistant sampling because the transmit
instruction is occurring on an SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N,
equidistant sampling is implemented by the DSP.
AD7452 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7452. The CS input allows easy interfacing between the
TMS320C5x/C54x and the AD7452 without any glue logic
required. The serial port of the TMS320C5x/C54x is set up to
operate in burst mode with internal CLKx (Tx serial clock) and
FSx (Tx frame sync). The serial port control register (SPC) must
have the following setup: FO = 0, FSM = 1, MCM = 1, and TxM
= 1. The format bit, FO, may be set to 1 to set the word length to
eight bits in order to implement the power-down mode on the
AD7452. The connection diagram is shown in Figure 41. It
should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the
TMS320C5x/C54x provides equidistant sampling.
AD7452*
TMS320C5x/
C54x*
CLKx
DR
FSx
FSR
SCLK
SDATA
CS
CLKR
03154-A
-041
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 41. Interfacing to the TMS320C5x/C54x
AD7452 to DSP56xxx
The connection diagram in Figure 42 shows how the AD7452
can be connected to the SSI (synchronous serial interface) of
the DSP56xxx family of DSPs from Motorola. The SSI is
operated in synchronous mode (SYN bit in CRB = 1) with
internally generated 1-word frame sync for both Tx and Rx
(Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word length to 16
by setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement
power-down mode on the AD7452, the word length can be
changed to eight bits by setting Bits WL1 = 0 and WL0 = 0 in
CRA. It should be noted that for signal processing applications,
it is imperative that the frame synchronization signal from the
DSP56xxx provides equidistant sampling.
AD7452*
DSP56xxx*
SCLK
SRD
SR2
SCLK
SDATA
CS
03154-A
-042
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 42. Interfacing to the DSP56xxx
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7452BRT-REEL | 制造商:Analog Devices 功能描述:ADC SGL SAR 555KSPS 12-BIT SERL 8PIN SOT-23 - Tape and Reel |
| AD7452BRT-REEL7 | 制造商:Analog Devices 功能描述: |
| AD7452BRTZ-R2 | 功能描述:IC ADC 12BIT 555KSPS SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7452BRTZ-REEL7 | 功能描述:IC ADC 12BIT DIF 555KSPS SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD7453 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Pseudo Differential, 555 kSPS, 12-Bit ADC in an 8-Lead SOT-23 |
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