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參數(shù)資料
| 型號： | AD7452BRT-R2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 555KSPS SOT23-8 |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 555k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應商設備封裝： | SOT-23-8 |
| 包裝： | 剪切帶 (CT) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
| 其它名稱： | AD7452BRT-R2CT |
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AD7452
Rev. B | Page 19 of 28
EXTERNAL
VREF (2.5V)
R
VIN+
VIN–
AD7452
5V
2.5V
0V
VREF
+2.5V
0V
–2.5V
VIN
R
0.1
F
R
03154-A
-034
Figure 34. Applying a Bipolar Single-Ended Input to the AD7452
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram for the serial interface
of the AD7452. The serial clock provides the conversion clock
and also controls the transfer of data from the device during
conversion. CS initiates the conversion process and frames the
data transfer. The falling edge of CS puts the track-and-hold
into hold mode and takes the bus out of three-state. The analog
input is sampled and the conversion is initiated at this point.
The conversion requires 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track on the next SCLK rising edge, as shown at
line goes back into three-state. If the rising edge of CS occurs
before 16 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state.
The conversion result from the AD7452 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7452 consists of four leading zeros followed by 12 bits of
conversion data provided MSB first. The output coding is twos
complement.
Sixteen serial clock cycles are required to perform a conversion
and access data from the AD7452. CS going low provides the
first leading zero to be read in by the microcontroller or DSP.
The remaining data is then clocked out on the subsequent
SCLK falling edges beginning with the second leading zero.
Thus, the first falling clock edge on the serial clock provides the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having been clocked out on the previous
(15th) falling edge. Once the conversion is complete and the data
has been accessed after the 16 clock cycles, it is important to
ensure that before the next conversion is initiated, enough time
is left to meet the acquisition, and quiet time specifications (see
the Timing Example).
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, i.e., the first rising edge of SCLK
after the CS falling edge would have the leading zero provided
and the 15th SCLK edge would have DB0 provided.
Timing Example
Having FSCLK = 10 MHz and a throughput rate of 555 kSPS gives
a cycle time of
1/Throughput = 1/555,000 = 1.8 s
A cycle consists of
t2 + 12.5(1/FSCLK) + tACQ = 1.8 s
Therefore, if t2 = 10 ns
10 ns + 12.5(1/10 MHz) + tACQ = 1.8 s
tACQ = 540 ns
This 540 ns satisfies the requirement of 290 ns for tACQ.
2.5(1/FSCLK) + t8 + tQUIET
where t8 = 35 ns. This allows a value of 255 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
t2
t8
t6
t5
tCONVERT
CS
SCLK
12
3
4
5
13
14
15
16
03154-A
-035
12.5(1/FSCLK)
tACQUISITION
1/THROUGHPUT
tQUIET
10ns
Figure 35. Serial Interface Timing Example
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7452BRT-REEL | 制造商:Analog Devices 功能描述:ADC SGL SAR 555KSPS 12-BIT SERL 8PIN SOT-23 - Tape and Reel |
| AD7452BRT-REEL7 | 制造商:Analog Devices 功能描述: |
| AD7452BRTZ-R2 | 功能描述:IC ADC 12BIT 555KSPS SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7452BRTZ-REEL7 | 功能描述:IC ADC 12BIT DIF 555KSPS SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應商設備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD7453 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Pseudo Differential, 555 kSPS, 12-Bit ADC in an 8-Lead SOT-23 |
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