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| 型號： | AD7452BRT-R2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 555KSPS SOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 555k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 剪切帶 (CT) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
| 其它名稱： | AD7452BRT-R2CT |
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AD7452
Rev. B | Page 20 of 28
MODES OF OPERATION
The mode of operation of the AD7452 is selected by controlling
the logic state of the CS signal during a conversion. There are
two possible modes of operation, normal and power-down. The
point at which CS is pulled high after the conversion has been
initiated determines whether or not the AD7452 enters the
power-down mode. Similarly, if already in power-down, CS
controls whether the device returns to normal operation or
remains in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for differing application requirements.
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7452 remaining fully powered up all the time. Figure 36
shows the general diagram of the AD7452’s operation in this
mode. The conversion is initiated on the falling edge of CS, as
described in the Serial Interface section. To ensure that the part
remains fully powered up, CS must remain low until at least 10
SCLK falling edges have elapsed after the falling edge of CS.
If CS is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part remains powered
up but the conversion is terminated and SDATA goes back into
three-state. Sixteen serial clock cycles are required to complete
the conversion and access the complete conversion result. CS
may idle high until the next conversion or may idle low until
sometime prior to the next conversion. Once a data transfer is
complete, i.e., when SDATA has returned to three-state, another
conversion can be initiated after the quiet time, tQUIET, has
elapsed by again bringing CS low.
110
CS
SCLK
SDATA
16
4 LEADING ZEROS + CONVERSION RESULT
03154-A
-036
Figure 36. Normal Mode Operation
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7452 is in power-
down mode, all analog circuitry is powered down. To enter
power-down mode, the conversion process must be interrupted
by bringing CS high anywhere after the second falling edge of
SCLK, and before the 10th falling edge of SCLK, as shown in
1
10
CS
SCLK
SDATA
THREE-STATE
2
03154-A
-037
Figure 37. Entering Power-Down Mode
Once CS has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of CS is terminated, and SDATA goes back into
three-state. The time from the rising edge of CS to SDATA
Specifications). If CS is brought high before the second SCLK
falling edge, the part remains in normal mode and does not
power down. This avoids accidental power-down due to glitches
on the CS line.
In order to exit this mode of operation and power up the
AD7452 again, a dummy conversion is performed. On the
falling edge of CS, the device begins to power up and continues
to power up as long as CS is held low until after the falling edge
of the 10th SCLK. The device is fully powered up after 1 s has
elapsed and, as shown in Figure 38, valid data results from the
next conversion.
If CS is brought high before the 10th falling edge of SCLK, the
AD7452 again goes back into power-down. This avoids acci-
dental power-up due to glitches on the CS line or an inadvertent
burst of eight SCLK cycles while CS is low. So although the
device may begin to power up on the falling edge of CS, it again
powers down on the rising edge of CS as long as it occurs before
the 10th SCLK falling edge.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7452BRT-REEL | 制造商:Analog Devices 功能描述:ADC SGL SAR 555KSPS 12-BIT SERL 8PIN SOT-23 - Tape and Reel |
| AD7452BRT-REEL7 | 制造商:Analog Devices 功能描述: |
| AD7452BRTZ-R2 | 功能描述:IC ADC 12BIT 555KSPS SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7452BRTZ-REEL7 | 功能描述:IC ADC 12BIT DIF 555KSPS SOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個(gè)單端，雙極；8 個(gè)差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD7453 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Pseudo Differential, 555 kSPS, 12-Bit ADC in an 8-Lead SOT-23 |
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