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參數(shù)資料
| 型號： | AD7367BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SAR 1MSPS 24TSSOP |
| 設計資源： | Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042) |
| 標準包裝： | 1,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 88.8mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極 |
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AD7366/AD7367
Rev. D | Page 25 of 28
Table 13. SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1)
Setting
Description
RCKFE = 1
Sample data with falling edge of RSCLK
LRFS = 1
Active low frame signal
RFSR = 1
Frame every word
IRFS = 1
Internal RFS used
RLSBIT = 0
Receive MSB first
RDTYPE = 00
Zero fill
IRCLK = 1
Internal receive clock
RSPEN = 1
Receive enabled
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word)
TFSR = RFSR = 1
Table 14. SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2)
Setting
Description
RXSE = 1
Secondary side enabled
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word)
AD7366/AD7367 TO TMS320VC5506
The serial interface on the TMS320VC5506 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices such as the
AD7366/AD7367. The CS input allows easy interfacing between
the TMS320VC5506 and the AD7366/AD7367 without any glue
logic required. The serial ports of the TMS320VC5506 are set
up to operate in burst mode with internal CLKX0 (Tx serial
clock on Serial Port 0) and FSX0 (Tx frame sync from Serial
Port 0). The serial port control (SPC) registers must be set up as
shown in Table 15.
Table 15. Serial Port Control Register Setup
SPC
FO
FSM
MCM
TXM
SPC0
0
1
SPC1
0
1
0
of the AD7366/AD7367 takes the same supply voltage as the
power supply pin of the TMS320VC5506. This allows the ADC
to operate at a higher voltage than its serial interface and,
therefore, the TMS320VC5506, if necessary.
FSR1
FSR0
AD7366/
AD7367*
SCLK
TMS320VC5506*
*ADDITIONAL PINS OMITTED FOR CLARITY.
CLKX0
DR1
CLKR1
CLKX1
DOUTB
DOUTA
VDRIVE
VDD
CS
FSX0
DR0
CLKR0
INTn
XF
CNVST
BUSY
06703-
033
Figure 31. Interfacing the AD7366/AD7367 to the TMS320VC5506
As with the previous interfaces, conversion can be initiated
from the TMS320VC5506 or from an external source, and the
processor is interrupted when the conversion sequence is
completed.
AD7366/AD7367 TO DSP563xx
The connection diagram in Figure 32 shows how the AD7366/
AD7367 can be connected to the enhanced synchronous serial
interface (ESSI) of the DSP563xx family of DSPs from Motorola.
There are two on-board ESSIs, and each is operated in synchro-
nous mode (Bit SYN = 1 in the CRB register) with internally
generated word length frame sync for both Tx and Rx (Bit
FSL1 = 0 and Bit FSL0 = 0 in the CRB register).
Normal operation of the ESSI is selected by setting MOD = 0 in
the CRB register. Set the word length to 16 by setting Bit WL1 = 1
and Bit WL0 = 0 in the CRA register. The FSP bit in the CRB
register should be set to 1 so that the frame sync is negative.
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