參數(shù)資料
型號(hào)： AD7367BRUZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SAR 1MSPS 24TSSOP
設(shè)計(jì)資源： Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 14
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 88.8mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極；4 個(gè)單端，雙極
AD7366/AD7367
Rev. D | Page 19 of 28
DRIVER AMPLIFIER CHOICE
The AD7366/AD7367 have a total of four analog inputs, which
operate in single-ended mode. The analog inputs for both ADCs
can be programmed to one of the three analog input ranges. In
applications where the signal source is high impedance, it is
recommended that the signal be buffered before applying it to
the ADC analog inputs. Figure 21 shows the configuration of
the AD7366/AD7367 in single-ended mode.
In applications where the THD and SNR are critical specifi-
cations, the analog input of the AD7366/AD7367 should be
driven from a low impedance source. Large source impedances
significantly affect the ac performance of the ADC and can
necessitate the use of an input buffer amplifier.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be tolerated
in the application. The THD increases as the source impedance
increases and performance degrades. Figure 7 shows THD vs.
the analog input frequency for various source impedances.
Depending on the input range and analog input configuration
selected, the AD7366/AD7367 can handle source impedances as
illustrated in Figure 7.
Due to the programmable nature of the analog inputs on the
AD7366/AD7367, the choice of op amp used to drive the
inputs is a function of the particular application and depends
on the analog input voltage range selected.
The driver amplifier must be able to settle for a full-scale step
to a 14-bit level, 0.0061%, in less than the specified acquisition
time of the AD7366/AD7367. An op amp such as the AD8021
meets this requirement when operating in single-ended mode.
The AD8021 needs an external compensating NPO type of
capacitor. The AD8022 can also be used in high frequency
applications where a dual version is required. For lower fre-
quency applications, recommended op amps are the AD797,
V+
V–
VDD
VSS
VA1
VCC
+5V
AGND
AD8021
1k
1k
15pF
CCOMP = 10pF
–10V/–5V
+10V/+5V
AD7366/
AD7367*
*ADDITIONAL PINS OMITTED FOR CLARITY.
10F
+
0.1F
+
0.1F
+
10F
+
06703-
023
Figure 21. Typical Connection Diagram with the AD8021 for Driving the
Analog Input
VDRIVE
The AD7366/AD7367 also have a VDRIVE feature to control the
voltage at which the serial interface operates. VDRIVE allows the
ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7366/AD7367 were operated with a VCC of
5 V, the VDRIVE pin could be powered from a 3 V supply, allowing
a large dynamic range with low voltage digital processors. Thus,
the AD7366/AD7367 can be used with the ±10 V input range
while still being able to interface to 3 V digital parts.
To achieve the maximum throughput rate of 1.12 MSPS for the
AD7366 or 1 MSPS for the AD7367, VDRIVE must be greater than
or equal to 4.75 V (see Table 2 and Table 3). The maximum
throughput rate with the VDRIVEvoltage set to less than 4.75 V
and greater than 2.7 V is 1 MSPS for the AD7366 and 900 kSPS
for the AD7367.
REFERENCE
The AD7366/AD7367 can operate with either the internal 2.5 V
on-chip reference or an externally applied reference. The logic
state of the REFSEL pin determines whether the internal refer-
ence is used. The internal reference is selected for both ADCs
when the REFSEL pin is tied to logic high. If the REFSEL pin is
tied to GND, an external reference can be supplied through the
DCAPA and DCAPB pins. On power-up, the REFSEL pin must be
tied to either a low or high logic state for the part to operate.
Suitable reference sources for the AD7366/AD7367 include the
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7366/
AD7367 in internal reference mode, the 2.5 V internal reference
is available at the DCAPA and DCAPB pins, which should be
decoupled to AGND using a 680 nF capacitor. It is recom-
mended that the internal reference be buffered before applying
it elsewhere in the system. The internal reference is capable of
sourcing up to 150 μA with an analog input range of ±10 V
and 70 μA for both the ±5 V and 0 V to 10 V ranges.
If the internal reference operation is required for the ADC con-
version, the REFSEL pin must be tied to logic high on power-up.
The reference buffer requires 70 s to power up and charge the
680 nF decoupling capacitor during the power-up time.
The AD7366/AD7367 are specified for a 2.5 V to 3 V reference.
When a 3 V reference is selected, the analog input ranges are
±12 V, ±6 V, and 0 V to 12 V. For these ranges, the VDD supply
must be greater than or equal to +12 V and the VSS supply must
be less than or equal to 12 V.
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