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參數(shù)資料
| 型號(hào)： | AD7367BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SAR 1MSPS 24TSSOP |
| 設(shè)計(jì)資源： | Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 88.8mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；4 個(gè)單端，雙極 |
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AD7366/AD7367
Rev. D | Page 20 of 28
MODES OF OPERATION
The mode of operation of the AD7366/AD7367 is selected by
the logic state of the CNVST signal at the end of a conversion.
There are two possible modes of operation: normal mode and
shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
Normal mode is intended for applications that require fast
throughput rates. In normal mode, the AD7366/AD7367
remain fully powered at all times, so the user does not need to
worry about power-up times. Figure 22 shows the general mode
of operation of the AD7366 in normal mode; Figure 23 shows
normal mode for the AD7367.
The conversion is initiated on the falling edge of CNVST as
described in the Circuit Information section. To ensure that
the part remains fully powered up at all times, CNVST must be
at logic state high before the BUSY signal goes low. If CNVST is
at logic state low when the BUSY signal goes low, the analog
circuitry powers down and the part ceases converting. The
BUSY signal remains high for the duration of the conversion.
The CS pin must be brought low to bring the data bus out of
three-state. Therefore, 12 SCLK cycles are required to read the
conversion result from the AD7366 and 14 SCLK cycles are
required to read the conversion result from the AD7367. The
DOUT lines return to three-state only when CS is brought high. If
CS is left low for an additional 12 SCLK cycles for the AD7366 or
14 SCLK cycles for the AD7367, the result from the other on-chip
and Figure 28 (see the Serial Interface section).
When 24 SCLK cycles have elapsed for the AD7366 or 28 SCLK
cycles for the AD7367, the DOUT line returns to three-state only
when CS is brought high, not on the 24th or 28th SCLK falling
edge. If CS is brought high prior to this, the DOUT line returns to
three-state at that point. Thus, CS must be brought high when
the read is completed, because the bus does not automatically
return to three-state upon completion of the dual result read.
When a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
the quiet time, tQUIET, has elapsed by bringing CNVST low again.
CNVST
BUSY
SCLK
t2
t1
t3
SERIAL READ OPERATION
CS
1
12
tCONVERT
tQUIET
06703-
024
Figure 22. Normal Mode Operation for the AD7366
BUSY
SCLK
t2
t1
t3
SERIAL READ OPERATION
CS
1
14
tCONVERT
tQUIET
06703-
025
CNVST
Figure 23. Normal Mode Operation for the AD7367
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| AD736AQ | 功能描述:IC TRUE RMS/DC CONV LP 8-CDIP RoHS:否 類別:集成電路 (IC) >> PMIC - RMS 至 DC 轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:46 系列:- 電流 - 電源:1.2mA 電源電壓:±18 V，36 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
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