參數(shù)資料
型號： AD7291BCPZ-RL7
廠商： Analog Devices Inc
文件頁數(shù)： 8/29頁
文件大?。?/td> 0K
描述： IC ADC I2C/SRL 22.22K 20LFCSP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 12
采樣率（每秒）： 22.22k
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 12.6mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 20-LFCSP-WQ（4x4）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個單端，單極
配用： EVAL-AD7291SDZ-ND - BOARD EVAL FOR AD7291
Data Sheet
AD7291
Rev. B | Page 15 of 28
INTERNAL REGISTER STRUCTURE
The AD7291 contains 34 internal registers (see Figure 23) that
are used to store conversion results, high and low conversion
limits, and information to configure and control the device.
There are 33 data registers and one address pointer register.
Each data register has an address that the address pointer
register points to when communicating with it. Table 9 details
which registers are read, write, or read/write.
ADDRESS POINTER REGISTER
The address pointer register is the register to which the first
data byte of every write operation is written automatically;
therefore, this register does not have and does not require an
address. The address pointer register is an 8-bit register in
which the six LSBs are used as pointer bits to store an address
that points to one of the AD7291’s data registers. The first byte
following each write address is to the address pointer register,
containing the address of one of the data registers. The six LSBs
select the data register to which subsequent data bytes are
written. Only the six LSBs of this register are used to select a
data register. During power-up, the address pointer register
contains all 0s, pointing to the command register.
Table 8. Address Pointer Register
D1
D0
P5
P4
P3
P2
P1
P0
0
Register select
SDA
SCL
DAT
A
COMMAND
REGISTER
TSENSE CONV
RESULT REGISTER
TSENSE AVG
RESULT REGISTER
CH0 DATAHIGH
REGISTER
CH1 DATALOW
REGISTER
CH0 HYSTERESIS
REGISTER
CH1 DATAHIGH
REGISTER
CH1 HYSTERESIS
REGISTER
CH0 DATALOW
REGISTER
CH7 DATAHIGH
REGISTER
CH7 DATALOW
REGISTER
CH7 HYSTERESIS
REGISTER
TSENSE HYSTERESIS
REGISTER
TSENSE DATAHIGH
REGISTER
TSENSE DATALOW
REGISTER
ALERT STATUS
REGISTER A
ALERT STATUS
REGISTER B
08
71
1-
01
5
VOLTAGE CONV
RESULT REGISTER
SERIAL BUS INTERFACE
ADDRESS
POINTER
REGISTER
Figure 23. AD7291 Register Structure
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