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參數(shù)資料
| 型號： | AD7291BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC I2C/SRL 22.22K 20LFCSP |
| 標準包裝： | 1,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 22.22k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.6mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 20-LFCSP-WQ（4x4） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
| 配用： | EVAL-AD7291SDZ-ND - BOARD EVAL FOR AD7291 |
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AD7291
Data Sheet
Rev. B | Page 26 of 28
AUTOCYCLE MODE
The AD7291 can be configured to convert continuously on a
programmable sequence of channels, making it the ideal mode
of operation for system monitoring. This mode is useful for
monitoring signals, such as battery voltage and temperature,
alerting only when the limits are violated.
Conversions take place in the background approximately every
50 μs, and are transparent to the master. The acquisition and
conversion times combined for any channel take approximately
3.6 μs. Typically, this mode is used to automatically monitor a
selection of channels with either the limit registers programmed
to signal an out-of-range condition via the alert function or the
minimum/maximum recorders tracking the variation over time
of a particular channel. Reads and writes can be performed at
any time (the ADC voltage conversion result register, Register
0x01, contains the most recent conversion result).
During power-up, this mode is disabled. To enable this mode,
write to Bit D0 in the command register (Register 0x00) and
select the desired channels for conversion by writing to the
corresponding channel bits (Bit D15 to Bit D8). If more than
one channel bit is set in the configuration register, the ADC
automatically cycles through the channel sequence starting with
the lowest channel and working its way up through the sequence.
Once the sequence is complete, the ADC starts converting on
the lowest channel again, continuing to loop through the
sequence until this mode is exited. Once a conversion is
completed, the conversion result is compared with the content
of the limit registers, and alert status registers are automatically
updated. If a violation of the limit registers is found, the ALERT
pin is asserted with the polarity determined by Bit D3 in the
command register.
If a command mode conversion is required while the autocycle
mode is active, it is necessary to disable the autocycle mode
before proceeding to the command mode. This is achieved
by setting Bit D0 of the command register to 1. When the
command mode conversion is complete, the user can reenable
autocycle mode by setting Bit D0 to 1 in the command register.
In autocycle mode, the AD7291 does not enter partial power-
down on receipt of a stop condition; therefore, conversions and
alert monitoring continue to function.
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