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參數(shù)資料
| 型號： | AD7291BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC I2C/SRL 22.22K 20LFCSP |
| 標準包裝： | 1,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 22.22k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.6mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-WQ（4x4） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
| 配用： | EVAL-AD7291SDZ-ND - BOARD EVAL FOR AD7291 |
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AD7291
Data Sheet
Rev. B | Page 20 of 28
HYSTERESIS REGISTER
Each analog input channel and the internal temperature sensor
has its own hysteresis register, which is a 16-bit read/write
register. Only the 12 LSBs are used. Bit D15 to Bit D12 are not
used in the register and are set to 0s. The hysteresis register
stores the hysteresis value, N, when using the limit registers.
Each pair of limit registers has a dedicated hysteresis register.
The hysteresis value determines the reset point for the ALERT
pin if a violation of the limits occurs. For example, if a hysteresis
value of eight LSBs is required on the upper and lower limits of
Channel 0, the 16-bit word, 0000 0000 0000 1000, should be
written to the hysteresis register of CH0, the address of which
hysteresis registers content defaults to all zeros (0x0000). If a
hysteresis value is required, that value must be written to the
hysteresis register for the channel in question.
Table 25. Hysteresis Register (First Read/Write Byte)
MSB
D15
D14
D13
D12
D11
D10
D9
D8
0
B11
B10
B9
B8
Table 26. Hysteresis Register (Second Read/Write Byte)
LSB
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
ALERT STATUS REGISTER A AND ALERT STATUS
REGISTER B (0x1F AND 0x20)
The alert status registers are 16-bit, read-only registers that
provide information on an alert event. If a conversion result
activates the ALERT pin, as described in the Limit Registers
(0x04 to 0x1E) section, the alert status register can be read to
gain further information. There are two alert status registers in
the AD7291; Alert Status Register A, which stores alerts for the
and Alert Status Register B, which stores alerts for the internal
Both alert status registers contain two status bits per channel,
one corresponding to the DATAHIGH limit and the other to the
DATALOW limit. The bit with a status of 1 shows where the
violation occurred—that is, on which channel—and whether
the violation occurred on the upper or lower limit. If a second
alert event occurs on the other channel between receiving the
first alert and interrogating the alert status register, the corres-
ponding bit for that alert event is also set. The entire contents
of the alert status register can be cleared by writing 1 to Bit D2
in the command register.
For example, if Bit D14 in Alert Status Register A is set to 1, the
lower limit on Channel 7 (Register 0x1A) has been violated,
while if Bit D11 is set 1, the upper limit on Channel 5 has been
violated (Register 0x13).
The TSENSEHIGH and TSENSE_AVGHIGH alerts are determined
by comparison with the TSENSE DATAHIGH register (Register
0x1C). Likewise, the TSENSELOW and TSENSE_AVGLOW alerts
are determined by comparison with the TSENSE DATALOW register
(Register 0x1D).
Table 27. Alert Status Register A (First Read Byte)
D15
D14
D13
D12
D11
D10
D9
D8
CH7HIGH
CH7LOW
CH6HIGH
CH6LOW
CH5HIGH
CH5LOW
CH4HIGH
CH4LOW
Table 28. Alert Status Register A (Second Read Byte)
D7
D6
D5
D4
D3
D2
D1
D0
CH3HIGH
CH3LOW
CH2HIGH
CH2LOW
CH1HIGH
CH1LOW
CH0HIGH
CH0LOW
Table 29. Alert Status Register B (First Read Byte)
D15
D14
D13
D12
D11
D10
D9
D8
0
Table 30. Alert Status Register B (Second Read Byte)
D7
D6
D5
D4
D3
D2
D1
D0
0
TSENSE_AVGHIGH
TSENSE_AVGLOW
TSENSEHIGH
TSENSELOW
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