參數(shù)資料
型號(hào)： AD7192BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/41頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 2CH W/PGA 24-TSSOP
產(chǎn)品培訓(xùn)模塊： Weigh Scale Introduction
設(shè)計(jì)資源： Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119)
標(biāo)準(zhǔn)包裝： 62
位數(shù)： 24
采樣率（每秒）： 4.8k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，單極；2 個(gè)差分，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極
產(chǎn)品目錄頁(yè)面： 777 (CN2011-ZH PDF)
AD7192
Rev. A | Page 11 of 40
Pin No.
Mnemonic
Description
13
AIN3
Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with
AIN4 or as a pseudodifferential input when used with AINCOM.
14
AIN4
Analog Input. This pin can be configured as the negative input of a fully differential input pair when used
with AIN3 or as a pseudodifferential input when used with AINCOM.
15
REFIN1(+)
Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(). REFIN1(+)
can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN1(+) REFIN1()), is
AVDD, but the part functions with a reference from 1 V to AVDD.
16
REFIN1()
Negative Reference Input. This reference input can lie anywhere between AGND and AVDD 1 V.
17
BPDSW
Bridge Power-Down Switch to AGND.
18
AGND
Analog Ground Reference Point.
19
DGND
Digital Ground Reference Point.
20
AVDD
Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with
AVDD at 5 V or vice versa.
21
DVDD
Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V
with DVDD at 5 V or vice versa.
22
SYNC
Logic input that allows for synchronization of the digital filters and analog modulators when using a number
of AD7192 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the
calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not
affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally
to DVDD.
23
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate
the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next
update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid
data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the
data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the
SCLK rising edge.
24
DIN
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers in the ADC, with the register selection bits of the communications register identifying the
appropriate register.
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