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參數(shù)資料
| 型號： | AD7192BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2CH W/PGA 24-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Weigh Scale Introduction |
| 設(shè)計(jì)資源： | Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個差分，單極；2 個差分，雙極；4 個偽差分，單極；4 個偽差分，雙極 |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
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AD7192
Rev. A | Page 37 of 40
APPLICATIONS INFORMATION
The AD7192 provides a low-cost, high resolution analog-to-
digital function. Because the analog-to-digital function is
provided by a Σ-Δ architecture, the part is more immune to
noisy environments, making it ideal for use in sensor
measurement and industrial and process control applications.
WEIGH SCALES
Figure 32 shows the AD7192 being used in a weigh scale
application. The load cell is arranged in a bridge network and
gives a differential output voltage between its OUT+ and OUT–
terminals. Assuming a 5 V excitation voltage, the full-scale
output range from the transducer is 10 mV when the sensitivity
is 2 mV/V. The excitation voltage for the bridge can be used to
directly provide the reference for the ADC because the reference
input range includes the supply voltage.
A second advantage of using the AD7192 in transducer-based
applications is that the bridge power-down switch can be fully
utilized to minimize the power consumption of the system. The
bridge power-down switch is connected in series with the cold
side of the bridge. In normal operation, the switch is closed and
measurements can be taken. In applications in which current
consumption is being minimized, the AD7192 can be placed in
standby mode, thus significantly reducing the power consumed
in the application. In addition, the bridge power-down switch
can be opened while in standby mode, thus avoiding unnecessary
power consumption by the front-end transducer. When the part
is taken out of standby mode and the bridge power-down switch
is closed, the user should ensure that the front end circuitry is
fully settled before attempting a read from the AD7192.
For simplicity, external filters are not included in Figure 32.
However, an R-C antialias filter must be included on each
analog input. This is required because the on-chip digital filter
does not provide any rejection around the modulator sampling
frequency or multiples of this frequency. Suitable values are a
100 Ω resistor in series with each analog input, a 0.1 μF
capacitor between the analog input pins, and a 0.01 μF
capacitor from each analog input pin to AGND.
MCLK1 MCLK2
P0/REFIN2(–) P1/REFIN2(+)
DVDD DGND
5V
AIN1
IN+
IN–
OUT–
OUT+
AIN2
AIN3
AIN4
AINCOM
REFIN1(–)
BPDSW
AGND
AD7192
REFIN1(+)
REFERENCE
DETECT
SERIAL
INTERFACE
AND
CONTROL
LOGIC
TEMP
SENSOR
CLOCK
CIRCUITRY
AVDD
AGND
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
AVDD
AGND
Σ-Δ
ADC
PGA
MUX
0
78
22
-02
4
Figure 32. Typical Application (Weigh Scale)
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