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參數(shù)資料
| 型號： | AD7192BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2CH W/PGA 24-TSSOP |
| 產品培訓模塊： | Weigh Scale Introduction |
| 設計資源： | Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) |
| 標準包裝： | 62 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個差分，單極；2 個差分，雙極；4 個偽差分，單極；4 個偽差分，雙極 |
| 產品目錄頁面： | 777 (CN2011-ZH PDF) |
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AD7192
Rev. A | Page 24 of 40
GPOCON REGISTER
(RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00)
The GPOCON register is an 8-bit register from which data can
be read or to which data can be written. This register is used to
enable the general-purpose digital outputs.
Table 21 outlines the bit designations for the GPOCON register.
GP0 through GP7 indicate the bit locations. GP denotes that the
bits are in the GPOCON register. GP7 denotes the first bit of
the data stream. The number in parentheses indicates the
power-on/reset default status of that bit.
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0(0)
BPDSW(0)
GP32EN(0)
GP10EN(0)
P3DAT(0)
P2DAT(0)
P1DAT(0)
P0DAT(0)
Table 21. Register Bit Designations
Bit Location
Bit Name
Description
GP7
0
This bit must be programmed with a Logic 0 for correct operation.
GP6
BPDSW
Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch
BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power–
down switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active.
GP5
GP32EN
Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the P3 and P2 digital outputs are
active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored.
GP4
GP10EN
Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the P1 and P0 digital outputs are
active. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are
ignored. The P1 and P0 pins can be used as a reference input to REFIN2 when the REFSEL bit in the
configuration register is set to 1.
GP3
P3DAT
Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin.
When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the
GPOCON register is read, the P3DAT bit reflects the status of the P3 pin if GP32EN is set.
GP2
P2DAT
Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin.
When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the
GPOCON register is read, the P2DAT bit reflects the status of the P2 pin if GP32EN is set.
GP1
P1DAT
Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin.
When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the
GPOCON register is read, the P1DAT bit reflects the status of the P1 pin if GP10EN is set.
GP0
P0DAT
Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin.
When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the
GPOCON register is read, the P0DAT bit reflects the status of the P0 pin if GP10EN is set.
OFFSET REGISTER
(RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000)
The offset register holds the offset calibration coefficient for the
ADC. The power-on reset value of the offset register is
0x800000. The AD7192 has four offset registers; therefore, each
channel has a dedicated offset register (see Table 20). Each of
these registers is a 24-bit read/write register. This register is
used in conjunction with its associated full-scale register to
form a register pair. The power-on reset value is automatically
overwritten if an internal or system zero-scale calibration is
initiated by the user. The AD7192 must be placed in power-
down mode or idle mode when writing to the offset register.
FULL-SCALE REGISTER
(RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0)
The full-scale register is a 24-bit register that holds the full-scale
calibration coefficient for the ADC. The AD7192 has four full-
scale registers; therefore, each channel has a dedicated full-scale
register (see Table 20). The full-scale registers are read/write
registers. However, when writing to the full-scale registers, the
ADC must be placed in power-down mode or idle mode. These
registers are configured at power-on with factory-calibrated
full-scale calibration coefficients, the calibration being performed
at gain = 1. Therefore, every device has different default coeffic-
ients. The default value is automatically overwritten if an
internal or system full-scale calibration is initiated by the user
or if the full-scale register is written to.
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