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參數(shù)資料
| 型號(hào)： | AD6652 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機(jī) |
| 文件頁數(shù)： | 64/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652 |
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AD6652
Table 28. M
Channel Addre
00
01
02
03
04
05
06
07
Rev. 0 | Page 64 of 76
p for Input Port Control Registers
Register
Lower Threshold A
Upper Threshold A
Dwell Time A
Gain Range A Control
Lower Threshold B
Upper Threshold B
Dwell Time B
Gain Range B Control Register
ss
Wid
mments
Co
9–0:
9–0:
19–0:
4:
3:
2–0:
9–0:
9–0:
19–0:
4:
3:
2–0:
emory Ma
Bit
10
10
20
5
10
10
20
5
th
Lower threshold for Input A
Upper threshold for Input A
Minimum time below Lower Threshold A
Output polarity LIA and LIA
(0) Reserved
Linearization hold-off register
Lower threshold for Input B
Upper threshold for Input B
Minimum time below Lower Threshold B
ity LIB and LIB
Output polar
(0) Reserved
Linearization hold-off register
ister
Reg
OUTPUT PORT CONTROL REGISTERS
roup o registers is dedicated to data management af
dual channels have processed the incoming data. The
nage data i
t port signment, and output port setu . Because the
re two outp t ports, A and B, the data must e funneled fr
ur channe down to two. These registers a
g the
ta directly to the proper outpu
uring th
ther post-filteri
nd so on) before the output port is selected
a
onsible for
ort(s) or
tages (AG
ng s
.
o access th output port registers for Outpu
f Externa
ddress 3 (the sleep register) m st be written logic
h. The ch nnel address register (CAR) is t en written wi
e address t the correct output port registe
mplete lis
g and brief description of all r isters.
0x07: Reserved
erved. Al
its should be written logic low
8: LHB
r
he acronym for interpolating half-band, with L bei
ly accepte
e interleaving stage as well as the half-band filter stage, as
own in Fi
e 64. These two stages are con olled separa
om the fin AGC stage, so that they do no
merous A C control elements.
nu
G
orts A and , Bit
t P
u
r. S
eg
ee Table 29 for a
et lost amon
t g
e
it 3, the LHB A enable bit, acts as an on/off
terleave st e, half-band filter, and the AGC stage. See
igure 64. If it 3 is low, the interleave stage is shut down a
ents any
ation of data to t
ages. This condition is desirable when the t ree stages are
eeded and ower conservation is desired. W en Bit 3 is h
e interleav
tage is active and works to int
p to four D
nd Bit 1. The data is then propagated to the LHB and AGC
ages with bypass opportunities included.
st
tch for the
swi
maining
eave the dat of
erl
B
table
h channels are interleaved. The truth
for these bits is shown in Table 29.
when high, directs data from the interleave
alf-band filter stage and proceed directly to
tage without interpolation. The channel data streams
ey are not filtered or interpolated. The
onfiguration is two times the
aximum data rate from this c
chip rate.
a
m
When Bit 0 is low, data from the interleave stage is passed
the half-band filter and undergoes a 2× interpolation
r
t data rate of the half-band is four
ti
mes the chip rate.
0x09: LHB B Control Register
ame as LHB A, except that only t
leaved. Ch
nable bit.
S
wo channels can be inter-
annels are selected using only Bit 1; Bit 2 is the LHB B
e
0x0A: AGC A Control Register
Bits 7–5 define the o
word can be 4 to 8, 10,
btain different output w
emory map, 0x0A.
m
utput word length of the AGC. The output
12, or 16 bits wide. The truth table to
ord lengths is given in the Table 29
o
of this register sets the mode of operation for the AGC.
he AGC tracks to maintain the output signal
s 1, the AGC tracks to maintain a constant
rror. See the Automatic Gain Control section for
odes.
etails about these two m
d
sed to configure the synchronization of the AGC.
The CIC decimator filter in the AGC can be directly synchro-
xternally generated signal. When synchronized, the
A
ple for the AGC error calculation
a
y, the AGC gain changes can be synchro-
nized to a Rake receiver.
This g
indivi
ma
outpu
a
fo
guidin
deto
ter
y
re
om
as
ls
da
e data through o
G
b
re resp
t p
C,
T
5 o
hig
th
co
0x00–
Res
0x0
LHB is t
wide
th
sh
fr
e
l A
tin
th
l b
A Control Registe
.
ng a
tely
g th
gur
al
tr
B
in
F
prev
st
n
th
u
a
B
further propag
nd
he re
not
igh,
t
p
e s
its 2 and 1 choose whic
Bit 0, the bypass bit,
stage to bypass the h
the AGC s
re still interleaved, but th
through
ate. The maximum outpu
Bit 4
When this bit is 0, t
level; when this bit i
clipping e
Bits 3–1 are u
nized to an e
GC outputs an update sam
nd filtering. This wa
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