參數(shù)資料
型號(hào)： AD6652
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 65 MSPS IF to Baseband Diversity Receiver
中文描述： 12位，65 MSPS的IF到基帶分集接收機(jī)
文件頁(yè)數(shù)： 61/76頁(yè)
文件大?。?/td> 1839K
代理商： AD6652
AD6652
M
rCIC2
must be chosen larger than L
rCIC2
, and both must be
chosen such that a
able rCIC2
deta
-Order RCIC Filter s
0x9
ation 1 (L
rCIC2
1
Thi
set the interpol
The
is register is the interpolation m
The rCI
u
f t
asso
terpolation. For deta
Order R
ion.
0x92: rCIC2 Scale
The rCI
er
co
Rev. 0 | Page 61 of 76
suit
scalar can be chosen. For
ection.
)
ation in the rCIC2 fil
ils, see the Second
1: rCIC2 Interpol
s register is used to
value written to th
C2 interpolation can range from 1 to 512, dependin
pon the decimation o he rCIC2. There is no timing error
ciated with this in
CIC Filter sect
inus
ils, see the Secon
C2 scale regist is used to provide attenuation to
mpensate for the gai of the rCIC2 and to adjust the linea i-
zation of the data from the floating-point input. The use of this
ale register is influenced by the rCIC2 growth. For details, see
sc
the Second-Order RCIC Filter section.
r,
ator,
ate for the
fth-Order CIC
1)
e
nus
p
d
be
el is synchronized,
it retains the phase setting chosen here. This can be used as part
of
overy loop with an external processor or can
al
ulti
p
0
F
The numbe
re
er.
0xA3: RCF Coeffici
T
iste
co
among mult
re
nced b
fere
y this pointer.
ile using a single RCF
t Filter section.
nus 1 is written to this
tion of the 256-word
o select
to memory and
T
(from the shadow register) on every new filter output sample.
This allows the coefficient offset to be written without
disturbing operation, even while a filter is being computed. Th
next sample that comes out of the RCF is
0xA4: RCF Control Register
The RCF control register is an 11-bit register that controls the
general features of the RCF as well as output formatting. The
bits of this register and their functions are described below.
iste
inter is updated
e
with the new filter.
sses the RCF filter and sends the CIC5 output data to
the BIST-I and BIST-Q registers. The 16 MSBs of the CIC5 data
can be accessed from this register, if Bit 9 of the output con
register at Channel Address 0xA9 is set.
trol
controls the source of the input data to the
processes the output data of its
t processes the data from the
own channel. If this bit is 1, then i
CIC5 of another channel. The CIC5 channels that the RCF c
be connected to when this bit is 1 are shown in the Table 26.
These can be us
process wider bandwidth channels
Table 26. RCF Input Configurations
Channel
RCF Input Source when Bit 9 Is 1
0
1
1
0
2
1
3
1
an
ed to allow multiple RCFs to be used together to
.
ter.
1.
g
d-
Bit 11 is reserved. Write all bits to Logic 0.
Bit 10 is reserved. Write all bits to Logic 0.
Bits 9–5 are the actual scale value used when the level indicato
LI pin associated with this channel, is active (Logic 1).
Bits 4–0 are the actual scale value used when the level indic
LI pin associated with this channel, is inactive (Logic 0).
0x93: Reserved
Eight bits, reserved (must be written low).
0x94: CIC5 Decimation – 1 (M
CIC5
1)
This register is used to set the decimation in the CIC5 filter. The
8-bit value written to this register is the decimation minus 1.
0x95: CIC5 Scale
The 5-bit CIC5 scale factor is used to compens
growth of the CIC5 filter. For details, see the Fi
Filter section.
0x96: Reserved
Reserved (must be written low).
0x97–0x9F: Unused
Unused.
0xA0: RCF Decimation 1 (M
RCF
This register is used to set the decimation of the RCF stage. Th
value written to this register is the desired decimation mi
one. Although this is an 8-bit register that allows decimation u
to 256, most filter designs should be limited to between 1 an
32. Higher decimations are allowed, but the alias rejection of the
RCF might not be acceptable for some applications.
0xA1: RCF Decimation Phase (P
RCF
)
This register allows any one of the M
RCF
phases of the filter to
used and can be adjusted dynamically. Each time a filter is
started, this phase is updated. When a chann
a timing rec
low m
air. For details, see the RAM Coefficien
xA2: RC Number of Tap – 1 (N
RCF
1)
r of taps for the RCF filter mi
gist
ent Offset (CO
RCF
)
his reg
r is used to specify which sec
efficien memory is used for a filter. It can be used t
iple filters that are loaded in
ple RCFs to work together wh
his reg
r is shadowed, and the filter po
Bit 10 bypa
Bit 9 of this register
RCF. If this bit is 0, then the RCF
Bit 8 is used as an extra address to allow a second block of
128 words of CMEM to be addressed by the channel addres
at 0x00–0x7F. If this bit is 0, then
if this bit is 1, then the next 128 words are written. This bit is
used to program only the coefficient memory so that filters
longer than 128 taps can be realized.
ses
the first 128 words are written;
hosen. These modes are enabled by
Bits 5 and 4 of this register. When this bit is 0, then the I and Q
output exponents are determined separately based on their
Bit 7 is used to control the output formatting of the AD6652’s
RCF data. This bit is used only when the 8 + 4 or 12 + 4
floating-point modes are c
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