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參數(shù)資料
| 型號： | AD6600ASTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL W/RSSI 44-LQFP T/R |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 976mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，雙極 |
REV. 0
–3–
AD6600
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS1
(AVCC = 5 V, DVCC = 3.3 V; ENC and
ENC = 20 MSPS; T
MIN = –40 C, TMAX = +85 C unless otherwise noted.)
Test
AD6600AST
Parameter
Name
Temp
Level
Min
Typ
Max
Unit
A/D CONVERTER
Conversion Rate
fENC
1/(tENC)
MSPS
Maximum Conversion Rate
Full
II
20
MSPS
Minimum Conversion Rate
Full
IV
6
MSPS
Aperture Uncertainty
tj
25
°C
V
0.3
ps rms
ENCODE INPUTS (ENC,
ENC)2
Period
tENC
Full
II
50
ns
Pulsewidth High
3
tENCH
Full
IV
20
ns
Pulsewidth Low
4
tENCL
Full
IV
20
ns
2
× CLOCK OUTPUT (CLK2×)5
Output Frequency
2
× fENC
MSPS
Output Period6
tCLK2×_1
Full
V
tENCL
ns
tCLK2×_2
Full
V
tENCH
ns
CLK2
× Pulsewidth Low6
tCLK2×L
Full
V
tENCH/2
ns
Output Risetime7
Full
V
3
ns
Output Falltime
7
Full
V
2.6
ns
OUTPUT RISE/FALL TIMES8
Output Risetime (D10:D0, RSSI2:0)
Full
V
8
ns
Output Falltime (D10:D0, RSSI2:0)
Full
V
8.4
ns
Output Risetime (AB_OUT)
Full
V
6
ns
Output Falltime (AB_OUT)
Full
V
6.2
ns
NOTES
1See AD6600 Timing Diagrams.
2All switching specifications tested by driving ENC and
ENC differentially.
3Several timing specifications are a function of Encode high time, t
ENCH; these specifications are shown in the data tables and timing diagrams. Encode duty cycle
should be kept as close to 50% as possible.
4Encode pulse low directly affects the amount of settling time available at FLT resonant port. See External Analog (Resonant) Filter section for details.
5The 2
× Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. All timing measurements to or from CLK2 × are
referenced to 2.0 V crossing.
6This specification IS a function of Encode period and duty cycle; reference timing diagrams Figure 8.
7Output rise time is measured from 20% point to 80% point of total CLK2
× voltage swing; output fall time is measured from 80% point to 20% point of total CLK2×
voltage swing.
8Output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% point to 20% point of total data voltage
swing. All outputs specified with 10 pF load.
Specifications subject to change without notice.
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