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參數(shù)資料
| 型號： | AD6600ASTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL W/RSSI 44-LQFP T/R |
| 標準包裝： | 1,500 |
| 位數(shù)： | 11 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 976mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應商設備封裝： | 44-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，雙極 |
REV. 0
–2–
AD6600–SPECIFICATIONS
DC SPECIFICATIONS
Test
AD6600AST
Parameter
Temp
Level
Min
Typ
Max
Unit
ANALOG INPUTS (AIN,
AIN/BIN, BIN)
Differential Analog Input Voltage Range1
Full
V
2.0
V p-p
Differential Analog Input Resistance
2
Full
IV
160
200
240
Differential Analog Input Capacitance
25
°C
V
1.5
pF
PEAK DETECTOR (Internal), RSSI
Resolution
3
Bits
RSSI Gain Step
Full
V
6
dB
RSSI Hysteresis
3
Full
V
6
dB
RESONANT PORT (FLT,
FLT)
Differential Port Resistance
Full
V
630
Differential Port Capacitance
Full
V
1.75
pF
A/D CONVERTER
Resolution
Full
IV
11
Bits
ENCODE INPUTS (ENC,
ENC)
Differential Input Voltage (AC-Coupled)
4
Full
IV
0.4
V p-p
Differential Input Resistance
25
°CV
11
k
Differential Input Capacitance
25
°C
V
2.5
pF
A/B MODE INPUTS (A_SEL, B_SEL)
5
Input High Voltage Range
Full
IV
4.75
5.25
V
Input Low Voltage Range
Full
IV
0.0
0.5
V
POWER SUPPLY
Supply Voltages
AVCC
Full
II
4.75
5.0
5.25
V
DVCC
Full
IV
3.0
3.3
5.25
V
Supply Current
IAVCC (AVCC = 5.0 V)
Full
II
145
182
mA
IDVCC (DVCC = 3.3 V)
Full
II
15
20
mA
POWER CONSUMPTION
6
Full
II
775
976
mW
NOTES
1Analog Input Range is a function of input frequency. See ac specifications for 70 MHz–250 MHz inputs.
2Analog Input Impedance is a function of input frequency. See ac specifications for 70 MHz–450 MHz inputs.
3Six dB of digital hysteresis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations.
4Encode inputs should be ac-coupled and driven differentially. See Encoding the AD6600 for details.
5A_SEL and B_SEL should be tied directly to ground or AVCC.
6Maximum power consumption is computed as maximum current at nominal supplies.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Test
AD6600AST
Parameter
Temp
Level
Min
Typ
Max
Unit
LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0)
1
Logic Compatibility
CMOS
Logic “1” Voltage (DVCC = 3.3 V)
Full
II
2.8
DVCC – 0.2
V
Logic “0” Voltage (DVCC = 3.3 V)
Full
II
0.2
0.5
V
Logic “1” Voltage (DVCC = 5.0 V)
Full
IV
4.0
DVCC – 0.35
V
Logic “0” Voltage (DVCC = 5.0 V)
Full
IV
0.35
0.5
V
Output Coding (D10–D0)
Two’s Complement
CLK2
× OUTPUT1, 2
Logic “1” Voltage (DVCC = 3.3 V)
Full
II
2.8
DVCC – 0.2
V
Logic “0” Voltage (DVCC = 3.3 V)
Full
II
0.2
0.5
V
Logic “1” Voltage (DVCC = 5.0 V)
Full
IV
4.0
DVCC – 0.3
V
Logic “0” Voltage (DVCC = 5.0 V)
Full
IV
0.35
0.5
V
NOTES
1Digital output load is one LCX gate.
2CLK2
× output voltage levels, high and low, tested at switching rate of 10 MHz.
Specifications subject to change without notice.
(AVCC = 5 V, DVCC = 3.3 V; TMIN = –40 C, TMAX = +85 C unless otherwise noted.)
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