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參數(shù)資料
| 型號(hào)： | AD5763CSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | DAC 16BIT DUAL 5V 2LSB 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5763/65 Metal Layer Edit Change 08/Sept/2009 |
| 設(shè)計(jì)資源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5763 (CN0074) |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 45mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，雙極 |
| 采樣率（每秒）： | * |
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AD5763
Data Sheet
Rev. C | Page 10 of 29
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
32
25
916
8
24
17
PIN 1
INDICATOR
AD5763
TOP VIEW
(Not to scale)
NC = NO CONNECT
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D0
D1
NC
VOUTA
AGNDA
AGNDB
VOUTB
NC
BI
N/
2sCO
M
P
AV
DD
AV
SS
TE
M
P
RE
F
G
ND
NC
RE
F
B
RE
F
A
RS
T
O
UT
RS
T
IN
DG
N
D
DV
CC
AV
DD
PG
N
D
AV
SS
IS
C
0
72
50
-00
6
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SYNC
Active Low Input. This pin is the frame synchronization signal for the serial interface. While SYNC is
low, data is transferred in on the falling edge of SCLK.
2
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin
operates at clock speeds up to 30 MHz.
3
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
4
SDO
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode.
51
CLR
Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.1
6
LDAC
Load DAC. Logic input. This pin is used to update the DAC registers and consequently the analog
outputs. When LDAC is tied permanently low, the addressed DAC register is updated on the rising
edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated but the
output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be
updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected.
7, 8
D0, D1
D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are confi-
gurable and readable over the serial interface. When configured as inputs, these pins have weak
internal pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
9
RSTOUT
Reset Logic Output. This pin is the output from the on-chip voltage monitor used in the reset
circuit. If desired, it can be used to control other system components.
10
RSTIN
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to
this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1.
Register values remain unchanged.
11
DGND
Digital Ground Pin.
12
DVCC
Digital Supply Pin. The voltage ranges from 2.7 V to 5.25 V.
13, 31
AVDD
Positive Analog Supply Pins. The voltage ranges from 4.75 V to 5.25 V.
14
PGND
Ground Reference Point for Analog Circuitry.
15, 30
AVSS
Negative Analog Supply Pins. The voltage ranges from –5.25 V to –4.75 V.
16
ISCC
This pin is used in association with an optional external resistor connected to AGND and programs
the short-circuit current of the output amplifiers. See the Design Features section for further details.
17, 18, 23, 24, 27
NC
No Connect.
19
VOUTB
Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
20
AGNDB
Ground Reference Pin for the DAC B Output Amplifier.
21
AGNDA
Ground Reference Pin for the DAC A Output Amplifier.
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| AD5764ASUZ | 功能描述:IC DAC 16BIT QUAD VOUT 32-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
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