參數(shù)資料
型號: AD5763CSUZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 10/28頁
文件大?。?/td> 0K
描述: DAC 16BIT DUAL 5V 2LSB 32-TQFP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD5763/65 Metal Layer Edit Change 08/Sept/2009
設計資源: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5763 (CN0074)
標準包裝: 500
設置時間: 8µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 雙 ±
功率耗散(最大): 45mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
供應商設備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電壓,雙極
采樣率(每秒): *
AD5763
Data Sheet
Rev. C | Page 18 of 28
TRANSFER FUNCTION
The output voltage expression for the AD5763 is given by
Table 7 shows the ideal input code to output voltage relationship
for the AD5763 for both offset binary and twos complement
data coding.
×
+
×
=
536
,
65
4
2
D
V
VOUTx
REFIN
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFA and REFB pins.
Table 7. Ideal Output Voltage to Input Code Relationship
Digital Input
Analog Output
Offset Binary Data Coding
ASYNCHRONOUS CLEAR (CLR)
MSB
LSB
VOUTx
1111
+2VREF × (32,767/32,768)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to keep CLR low
for a minimum amount of time for the operation to complete (see
). When the
CLR signal is returned high, the output
remains at the cleared value until a new value is programmed.
If at power-on, CLR is at 0 V, all DAC outputs are updated with
the clear value. A clear can also be initiated through software by
writing a command, 0x04XXXX, to the AD5763.
1000
0000
0001
+2VREF × (1/32,768)
1000
0000
0 V
0111
1111
2VREF × (1/32,768)
0000
2VREF × (32,767/32,768)
Twos Complement Data Coding
MSB
LSB
VOUTx
0111
1111
+2VREF × (32,767/32,768)
0000
0001
+2VREF × (1/32,768)
0000
0 V
1111
2VREF × (1/32,768)
1000
0000
2VREF × (32,767/32,768)
Table 8. Input Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15:DB0
R/W
0
REG2
REG1
REG0
A2
A1
A0
Data
Table 9. Input Register Bit Functions
Bit
Description
R/W
Indicates a read from or a write to the addressed register
REG2, REG1, REG0
These bits are used in association with the address bits to determine if a read or write operation is sent to the
function register, data register, offset register, or gain register
REG2
REG1
REG0
Function
0
Function register
0
1
0
Data register
0
1
Coarse gain register
1
0
Fine gain register
1
0
1
Offset register
A2, A1, A0
These bits are used to decode the DAC channels
A2
A1
A0
Channel Address
0
DAC A
0
1
DAC B
1
0
Both DACs
D15:D0
Data bits
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