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| 型號(hào)： | AD5763CSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 19/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | DAC 16BIT DUAL 5V 2LSB 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5763/65 Metal Layer Edit Change 08/Sept/2009 |
| 設(shè)計(jì)資源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5763 (CN0074) |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 45mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，雙極 |
| 采樣率（每秒）： | * |
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AD5763
Data Sheet
Rev. C | Page 26 of 28
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board (PCB) on which
the AD5763 is mounted should be designed so that the analog
and digital sections are separated and confined to certain areas
of the board. If the AD5763 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. Establish the star ground point as
close as possible to the device. The AD5763 should have ample
supply bypassing of 10 μF in parallel with 0.1 μF on each supply
located as close to the package as possible, ideally right up against
the device. The 10 μF capacitors are the tantalum bead type. The
0.1 μF capacitor should have low effective series resistance (ESR)
and low effective series inductance (ESI) such as the common
ceramic types, which provide a low impedance path to ground at
high frequencies to handle transient currents due to internal logic
switching.
The power supply lines of the AD5763 should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals, such as clocks, should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk between
them. This is not required on a multilayer board, which has a
separate ground plane, however, it is helpful to separate the
lines. It is essential to minimize noise on the reference inputs,
because it couples through to the DAC output. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces
the effects of feedthrough on the board. A microstrip technique
is recommended, but not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground plane and signal traces are placed on the
solder side.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that might occur. Iso-
couplers provide voltage isolation in excess of 2.5 kV. The serial
loading structure of the AD5763 makes it ideal for isolated
interfaces because the number of interface lines is kept to a
minimum. Figure 30 shows a 4-channel isolated interface to
the AD5763 using an ADuM1400.
VIA
SERIAL CLOCK
OUT
TO SCLK
VOA
ENCODE
DECODE
VIB
SERIAL DATA
OUT
TO SDIN
VOB
ENCODE
DECODE
VIC
SYNC OUT
VOC
ENCODE
DECODE
VID
CONTROL OUT
VOD
ENCODE
DECODE
MICRO-
CONTROLLER
ADuM14001
1ADDITIONAL PINS OMITTED FOR CLARITY.
TO SYNC
TO LDAC
07250-
0
36
Figure 30. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5763 is via a serial
bus using a standard protocol that is compatible with micro-
controllers and DSP processors. The communications channel
is a 3-wire minimum interface consisting of a clock signal, a
data signal, and a synchronization signal. The AD5763 requires
a 24-bit data-word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in, or it can be done
under the control of LDAC. The contents of the DAC register
can be read using the readback function.
AD5763 to Blackfin DSP Interface
Figure 31 shows how the AD5763 can be interfaced to an Analog
Devices, Inc., Blackfin DSP. The Blackfin has an integrated SPI
port that can be connected directly to the SPI pins of the AD5763
and programmable I/O pins that can be used to set the state of a
digital input such as the LDAC pin.
ADSP-BF531
AD5763
SYNC
SPISELx
SCLK
SCK
SDIN
MOSI
LDAC
PF10
07
25
0-
0
39
Figure 31. AD5763 to Blackfin Interface
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| AD5764ASUZ | 功能描述:IC DAC 16BIT QUAD VOUT 32-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD5764ASUZ-REEL7 | 功能描述:IC DAC 16BIT QUAD VOUT 32-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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