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參數(shù)資料
| 型號(hào)： | AD5763CSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | DAC 16BIT DUAL 5V 2LSB 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5763/65 Metal Layer Edit Change 08/Sept/2009 |
| 設(shè)計(jì)資源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5763 (CN0074) |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 45mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，雙極 |
| 采樣率（每秒）： | * |
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Data Sheet
AD5763
Rev. C | Page 23 of 28
LOCAL GROUND OFFSET ADJUST
The AD5763 incorporates a local-ground-offset adjust feature
which, when enabled in the function register, adjusts the DAC
outputs for voltage differences between the individual DAC
ground pins and the REFGND pin ensuring that the DAC
output voltages are always with respect to the local DAC
ground pin. For instance, if Pin AGNDA is at 5 mV with
respect to the REFGND pin and VOUTA is measured with
respect to AGNDA, then a 5 mV error results, enabling the
local-ground-offset adjust feature which adjusts VOUTA by
+5 mV, eliminating the error.
POWER-ON STATUS
The AD5763 has multiple power supply and digital input pins.
It is important to consider the sequence in which the pins are
powered up to ensure the AD5763 powers-on in the required
state. The outputs will power-on either clamped to AGNDx,
driving 0 V, or driving negative full-scale output (4.096 V)
depending on how the BIN/2sCOMP, CLR, and LDAC pins
are configured during power-up. If the CLR pin is connected to
DGND, it causes the DAC registers to be loaded with 0x0000
and the outputs to be updated. Consequently, the outputs are
loaded with 0 V if BIN/2sCOMP is connected to DGND or
negative full-scale (4.096 V) if BIN/2sCOMP is connected to
DVCC corresponding respectively to the twos complement and
binary voltages for the digital code 0x0000. During power-up
the state of the LDAC pin has an identical effect to that of the
CLR pin. If both the CLR and LDAC pins are connected to
DVCC during power-up the outputs power-on clamped to
AGNDx and remain so until a valid write is made to the device.
outlines the possible output power-on states.
Table 19. Output Power-On State
BIN/2sCOMP
CLR
LDAC
VOUT at Power-On
DGND
0 V
DGND
DVCC
0 V
DGND
DVCC
DGND
0 V
DGND
DVCC
Clamped to AGNDx
DVCC
DGND
4.096 V
DVCC
DGND
DVCC
4.096 V
DVCC
DGND
4.096 V
DVCC
Clamped to AGNDx
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD5763CSUZ-TR | 制造商:Analog Devices 功能描述:16BIT +/-5V DUAL 1LSB - Tape and Reel |
| AD5764 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC |
| AD5764ASU | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC |
| AD5764ASUZ | 功能描述:IC DAC 16BIT QUAD VOUT 32-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD5764ASUZ-REEL7 | 功能描述:IC DAC 16BIT QUAD VOUT 32-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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