參數(shù)資料
型號： AD5762RCSUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 17/32頁
文件大?。?/td> 0K
描述： IC DAC 16BIT QUAD VOUT 32-TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5762R Metal Layer Edit Change 07/Sept/2009
標(biāo)準(zhǔn)包裝： 500
設(shè)置時間： 8µs
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 180mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電壓，雙極
采樣率（每秒）： 84.6k
AD5762R
Data Sheet
Rev. C | Page 24 of 32
REGISTERS
Table 9. Input Shift Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB0
R/W
0
REG2
REG1
REG0
A2
A1
A0
Data
Table 10. Input Shift Register Bit Function Descriptions
Register Bit
Descriptions
R/W
Indicates a read from or a write to the addressed register
REG2, REG1, REG0
Used in association with the address bits, determines if a read or write operation is to the data register, offset
register, gain register, or function register
REG2
REG1
REG0
Function
0
Function register
0
1
0
Data register
0
1
Coarse gain register
1
0
Fine gain register
1
0
1
Offset register
A2, A1, A0
Decodes the DAC channels
A2
A1
A0
Channel Address
0
DAC A
0
1
DAC B
1
0
Both DACs
Data
Data bits
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 11 and Table 12.
Table 11. Function Register Options
REG2
REG1
REG0
A2
A1
A0
DB15 to DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
NOP, data = don’t care
0
1
Don’t care
Local ground
offset adjust
D1
direction
D1
value
D0
direction
D0
value
SDO
disable
0
1
0
Clear, data = don’t care
0
1
0
1
Load, data = don’t care
Table 12. Explanation of Function Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Local Ground Offset Adjust
Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local
ground offset adjust function (default). See the Design Features section for more information.
D0, D1 Direction
Set by the user to enable the D0 and D1 pins as outputs. Cleared by the user to enable the D0 and D1 pins
as inputs (default). See the Design Features section for more information.
D0, D1 Value
I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1
pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is
active as an input. When enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Clear
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in
binary mode.
Load
Addressing this function updates the DAC registers and, consequently, the analog outputs.
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