參數(shù)資料
型號(hào)： AD5757ACPZ
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 15 us SETTLING TIME, 16-BIT DAC, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁(yè)數(shù)： 32/44頁(yè)
文件大?。?/td> 1122K
代理商： AD5757ACPZ
AD5757
Rev. A | Page 38 of 44
0
4
12
8
16
24
20
28
32
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
0.5
1.0
1.5
2.0
2.5
I OU
T
_x
CURRE
NT
(m
A
)/
V
BO
O
S
T_
xVO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
092
25
-18
5
Figure 59. AICC Current vs. Time for 24 mA Through 1 kΩ Slew with External
51 kΩ Compensation Resistor
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(A)
0mA TO 24mA RANGE
500 LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
4
12
8
16
24
20
28
32
0
0.5
1.0
1.5
2.0
2.5
I OU
T
_x
CURRE
NT
(m
A
)/
V
BO
O
S
T_
xVO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
092
25
-18
6
Figure 60. AICC Current vs. Time for 24 mA Through 500 Ω Slew with External
51 kΩ Compensation Resistor
Using slew rate control can greatly reduce the AVCC supplies
current requirements, as shown in Figure 61. When using slew
rate control, attention should be paid to the fact that the output
cannot slew faster than the dc-to-dc converter. The dc-to-dc
converter slews slowest at higher currents through large (for
example, 1 kΩ) loads. This slew rate is also dependent on the
configuration of the dc-to-dc converter. Two examples of the
dc-to-dc converter’s output slew are shown in Figure 59 and
Figure 60 (VBOOST corresponds to the dc-to-dc converter’s output
voltage).
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
4
12
8
16
24
20
28
32
0
1
2
345
6
I OU
T
_x
CURRE
NT
(m
A
)/
V
BO
O
S
T_
xVO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
092
25
-18
7
Figure 61. AICC Current vs. Time for 24 mA Slew with Slew Rate Control
EXTERNAL PMOS MODE
The AD5757 can also be used with an external PMOS transistor
per channel, as shown in Figure 62. This mode can be used to
limit the on-chip power dissipation of the AD5757, though this
will not reduce the power dissipation of the total system. The
IGATE functionality is not typically required when using the
dynamic power control feature so Figure 62 shows the
configuration of the device for a fixed VBOOST_x supply.
In this configuration the SWx pin are left floating and the
GNDSWx pin is grounded. The VBOOST_x pin is connected to a
minimum supply of 7.5 V and a maximum supply of 33 V. This
supply can be sized according to the maximum load required to
be driven.
The IGATE functionality works by holding the gate of the
external PMOS transistor at (VBOOST_x 5 V). This means that
the majority of the channels power dissipation will take place in
this external PMOS transistor.
The external PMOS transistor should be chosen tolerate a VDS
voltage of at least VBOOST_x, as well as to handle the power
dissipation required. This external PMOS transistor typically
has minimal effect on the current output performance.
09
22
5-
1
90
R1
R2
R3
RSET_A
RLOAD
SWGNDA
VBOOST_A
(VBOOST_A –5V)
SWA
CHARTA
IGATEA
CURRENT OUTPUT
DAC CHANNEL A
(LEFT FLOATING)
IOUT_A
DAC A
5.0V
AVCC
Figure 62. Configuration off a Particular Channel Using IGATE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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