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參數(shù)資料
型號(hào)： AD5737ACPZ
廠商： Analog Devices Inc
文件頁數(shù)： 33/44頁
文件大?。?/td> 0K
描述： IC DAC QUAD 12BIT CUR 64-LFCSP
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 15µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： *
Data Sheet
AD5737
Rev. C | Page 39 of 44
Using Slew Rate Control
Using slew rate control can greatly reduce the current require-
ments of the AVCC supply, as shown in Figure 60.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
4
12
8
16
24
20
28
32
0
1
2
345
6
I OU
T
_x
CURRE
NT
(
m
A
)/
V
BO
O
S
T
_x
VOL
TA
G
E
(V
)
TIME (ms)
AICC
IOUT
VBOOST
10
06
7-
18
7
Figure 60. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load
with Slew Rate Control
When using slew rate control, it is important to remember that
the output cannot slew faster than the dc-to-dc converter. The
dc-to-dc converter slews slowest at higher currents through
large loads (for example, 1 kΩ). The slew rate is also dependent
on the configuration of the dc-to-dc converter. Two examples of
the dc-to-dc converter output slew are shown in Figure 58 and
Figure 59. (VBOOST corresponds to the output voltage of the
dc-to-dc converter.)
EXTERNAL PMOS MODE
The AD5737 can also be used with an external PMOS transistor
per channel, as shown in Figure 61. This mode can be used to
limit the on-chip power dissipation of the AD5737, although this
mode does not reduce the power dissipation of the total system.
The IGATEx functionality is not typically required when using
the dynamic power control feature; therefore, Figure 61 shows
the configuration of the device for a fixed VBOOST_x supply.
In this configuration, the SWx pin is left floating, and the GNDSWx
pin is grounded. The VBOOST_x pin is connected to a minimum
supply of 7.4 V and a maximum supply of 33 V. This supply can
be sized according to the maximum load required to be driven.
The IGATEx functionality works by holding the gate of the
external PMOS transistor at (VBOOST_x 5 V). This means that
the majority of the channel’s power dissipation takes place in
the external PMOS transistor.
The external PMOS transistor should be selected to tolerate a
VDS voltage of at least the VBOOST_x voltage, as well as to handle
the power dissipation required. The external PMOS transistor
typically has minimal effect on the current output performance.
10
06
7-
19
0
R1
R2
R3
RSET_A
RLOAD
GNDSWA
VBOOST_A
(VBOOST_A – 5V)
SWA
CHARTA
IGATEA
CURRENT OUTPUT
DAC CHANNEL A
(LEFT FLOATING)
IOUT_A
DAC A
5.0V
AVCC
Figure 61. Configuration of Channel A Using IGATEx
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