AICC SUPPLY REQUIREMENTS—SLEWING
參數(shù)資料
型號(hào)： AD5737ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/44頁(yè)
文件大?。?/td> 0K
描述： IC DAC QUAD 12BIT CUR 64-LFCSP
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 15µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
輸出數(shù)目和類(lèi)型： 4 電流，單極
采樣率（每秒）： *
AD5737
Data Sheet
Rev. C | Page 38 of 44
AICC SUPPLY REQUIREMENTS—SLEWING
The AICC current requirement while slewing is greater than in
static operation because the output power increases to charge
the output capacitance of the dc-to-dc converter. This transient
current can be quite large (see Figure 57), although the methods
can reduce the requirements on the AVCC supply.
If not enough AICC current can be provided, the AVCC voltage
drops. Due to this AVCC drop, the AICC current required for
slewing increases further, causing the voltage at AVCC to drop
further (see Equation 3). In this case, the VBOOST_x voltage and,
therefore, the output voltage, may never reach their intended
values. Because the AVCC voltage is common to all channels,
this voltage drop may also affect other channels.
0
5
10
15
20
25
30
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0.5
1.0
1.5
2.0
2.5
I O
UT
_
x
CURRE
NT
(
m
A)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
AI
CC
CURRE
NT
(
A)
TIME (ms)
AICC
IOUT
VBOOST
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
10067-
184
Figure 57. AICC Current vs. Time for 24 mA Step Through 1 k Load
with Internal Compensation Resistor
Reducing AICC Current Requirements
Two main methods can be used to reduce the AICC current
requirements. One method is to add an external compensation
resistor, and the other is to use slew rate control. These methods
can be used together.
Adding an External Compensation Resistor
A compensation resistor can be placed at the COMPDCDC_x pin
in series with the 10 nF compensation capacitor. A 51 k exter-
nal compensation resistor is recommended. This compensation
increases the slew time of the current output but reduces the AICC
transient current requirements. Figure 58 shows a plot of AICC
current for a 24 mA step through a 1 k load when using a 51 k
compensation resistor. The compensation resistor reduces the
current requirements through smaller loads even further, as
shown in Figure 59.
0
4
12
8
16
24
20
28
32
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
0.5
1.0
1.5
2.0
2.5
I O
UT
_
x
CURRE
NT
(
m
A)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
10067-
185
Figure 58. AICC Current vs. Time for 24 mA Step Through 1 k Load
with External 51 k Compensation Resistor
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
500 LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
4
12
8
16
24
20
28
32
0
0.5
1.0
1.5
2.0
2.5
I O
UT
_
x
CURRE
NT
(
m
A)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
10067-
186
Figure 59. AICC Current vs. Time for 24 mA Step Through 500 Load
with External 51 k Compensation Resistor
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