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| 型號： | AD5737ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/44頁 |
| 文件大小： | 0K |
| 描述： | IC DAC QUAD 12BIT CUR 64-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 15µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | * |
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AD5737
Data Sheet
Rev. C | Page 36 of 44
When the slew rate control feature is enabled, all output changes
occur at the programmed slew rate (see the DC-to-DC Converter
Settling Time section for more information). For example, if the
CLEAR pin is asserted, the output slews to the clear value at the
programmed slew rate (assuming that the channel is enabled to
be cleared).
If more than one channel is enabled for digital slew rate control,
care must be taken when asserting the CLEAR pin. If a channel
under slew rate control is slewing when the CLEAR pin is asserted,
other channels under slew rate control may change directly to
their clear code not under slew rate control.
DYNAMIC POWER CONTROL
The AD5737 provides integrated dynamic power control using
a dc-to-dc boost converter circuit. This circuit reduces power
consumption compared with standard designs.
In standard current input module designs, the load resistor
values can range from typically 50 to 750 . Output module
systems must source enough voltage to meet the compliance
voltage requirement across the full range of load resistor values.
For example, in a 4 mA to 20 mA loop when driving 20 mA, a
compliance voltage of >15 V is required. When driving 20 mA
into a 50 load, a compliance voltage of only 1 V is required.
The AD5737 circuitry senses the output voltage and regulates
this voltage to meet the compliance requirements plus a small
headroom voltage. The AD5737 is capable of driving up to
24 mA through a 1 k load.
DC-TO-DC CONVERTERS
The AD5737 contains four independent dc-to-dc converters.
These are used to provide dynamic control of the VBOOST_x supply
voltage for each channel (see Figure 48). Figure 55 shows the
discrete components needed for the dc-to-dc circuitry, and the
following sections describe component selection and operation
of this circuitry.
AVCC
LDCDC
DDCDC
CDCDC
4.7F
CFILTER
0.1F
RFILTER
CIN
SWx
VBOOST_x
≥10F
10
10H
10067-
077
Figure 55. DC-to-DC Circuit
Table 36. Recommended Components for a DC-to-DC Converter
Symbol
Component
Value
Manufacturer
L
DCDC
XAL4040-103
10 H
Coilcraft
C
DCDC
GRM32ER71H475KA88L
4.7 F
Murata
D
DCDC
PMEG3010BEA
0.285 V
F
NXP
It is recommended that a 10 , 100 nF low-pass RC filter be
placed after CDCDC. This filter consumes a small amount of power
but reduces the amount of ripple on the VBOOST_x supply.
DC-to-DC Converter Operation
The on-board dc-to-dc converters use a constant frequency, peak
current mode control scheme to step up an AVCC input of 4.5 V
to 5.5 V to drive the AD5737 output channel. These converters
are designed to operate in discontinuous conduction mode with
a duty cycle of <90% typical. Discontinuous conduction mode
refers to a mode of operation where the inductor current goes
to zero for an appreciable percentage of the switching cycle. The
dc-to-dc converters are nonsynchronous; that is, they require an
external Schottky diode.
DC-to-DC Converter Output Voltage
When a channel current output is enabled, the converter regulates
the VBOOST_x supply to 7.4 V (±5%) or (IOUT × RLOAD + Headroom),
whichever is greater (see Figure 30 for a plot of headroom supplied
vs. output current). When the output is disabled, the converter
regulates the VBOOST_x supply to 7.4 V (±5%).
DC-to-DC Converter Settling Time
The settling time for a step greater than ~1 V (IOUT × RLOAD) is
dominated by the settling time of the dc-to-dc converter. The
exception to this is when the required voltage at the IOUT_x pin
plus the compliance voltage is below 7.4 V (±5%). Figure 25
shows a typical plot of the output settling time. This plot is for
a 1 k load. The settling time for smaller loads is faster. The
settling time for current steps less than 24 mA is also faster.
DC-to-DC Converter VMAX Functionality
The maximum VBOOST_x voltage is set in the dc-to-dc control
register (23 V, 24.5 V, 27 V, or 29.5 V; see Table 27). When the
maximum voltage is reached, the dc-to-dc converter is disabled,
and the VBOOST_x voltage is allowed to decay by ~0.4 V. After the
VBOOST_x voltage decays by ~0.4 V, the dc-to-dc converter is
reenabled, and the voltage ramps up again to VMAX, if still
required. This operation is shown in Figure 56.
28.6
28.7
28.8
28.9
29.0
29.1
29.2
29.3
29.4
29.5
29.6
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
TIME (ms)
VMAX
0mA TO 24mA RANGE, 24mA OUTPUT
OUTPUT UNLOADED
DC-DC MaxV BITS = 29.5V
DC-DCx BIT
DC-DCx BIT = 0
DC-DCx BIT = 1
f
SW = 410kHz
TA = 25°C
10067-
183
Figure 56. Operation on Reaching VMAX
As shown in Figure 56, the DC-DCx bit in the status register
is deasserted when the voltage decays to VMAX ~0.4 V.
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