參數(shù)資料
型號(hào)： AD5735ACPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/48頁(yè)
文件大?。?/td> 0K
描述： IC DAC QUAD VOLT CUR 64LFCSP
標(biāo)準(zhǔn)包裝： 750
設(shè)置時(shí)間： 18µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，4 電壓
采樣率（每秒）： *
AD5735
Data Sheet
Rev. C | Page 34 of 48
CONTROL REGISTERS
When writing to a control register, the format shown in Table 19
must be used. See Table 12 for information about the configura-
tion of Bit D23 to Bit D16. The control registers are addressed
by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift
register) to 111 and then setting the CREG[2:0] bits to select the
specific control register (see Table 20).
Main Control Register
The main control register options are shown in Table 21 and
Table 22. See the Device Features section for more information
about the features controlled by the main control register.
Table 19. Input Shift Register for a Write Operation to a Control Register
MSB
LSB
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12 to D0
R/W
DUT_AD1
DUT_AD0
1
DAC_AD1
DAC_AD0
CREG2
CREG1
CREG0
Data
Table 20. Control Register Addresses (CREG[2:0] Bits)
CREG2 (D15)
CREG1 (D14)
CREG0 (D13)
Control Register
0
Slew rate control register (one per channel)
0
1
Main control register
0
1
0
DAC control register (one per channel)
0
1
DC-to-DC control register
1
0
Software register
Table 21. Programming the Main Control Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3 to D0
0
1
POC
STATREAD
EWD
WD1
WD0
X1
ShtCctLim
OUTEN_ALL DCDC_ALL
X1
1 X = don’t care.
Table 22. Main Control Register Bit Descriptions
Bit Name
Description
POC
The POC bit determines the state of the voltage output channels during normal operation.
POC = 0: the output goes to the value set by the POC hardware pin when the voltage output is not enabled (default).
POC = 1: the output goes to the opposite value of the POC hardware pin when the voltage output is not enabled.
STATREAD
Enable status readback during a write. See the Status Readback During a Write section.
0 = disable status readback (default).
1 = enable status readback.
EWD
Enable the watchdog timer. See the Watchdog Timer section.
0 = disable the watchdog timer (default).
1 = enable the watchdog timer.
WD1, WD0
Timeout select bits. Used to select the timeout period for the watchdog timer.
WD1
WD0
Timeout Period (ms)
0
5
0
1
10
1
0
100
1
200
ShtCctLim
Programmable short-circuit limit on the V
OUT_x pin in the event of a short-circuit condition.
0 = 16 mA (default).
1 = 8 mA.
OUTEN_ALL
Setting this bit to 1 enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the
OUTEN bit in the DAC control register.
DCDC_ALL
Setting this bit to 1 powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc
converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the
DAC control register.
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