參數(shù)資料
型號(hào)： AD5380BST-3
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC
中文描述： PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100
封裝： 14 X 14 MM, MS-026BED, LQFP-100
文件頁(yè)數(shù)： 25/34頁(yè)
文件大?。?/td> 975K
代理商： AD5380BST-3
PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
AD5380
–25–
I2C SERIAL INTERFACE
The AD5380 features an I2C compatible 2-wire interface consisting of a serial data line (SDA) and
a serial clock line (SCL). SDA and SCL facilitate communication between the AD5380 and the master at rates up to
400kHz. Figure 5,6 and shows the 2-wire interface timing diagrams that incorporate three different modes of operation.
In selecting the I2C operating mode firstly configure serial operating mode (SER/
PAR
=1) and then select I2C mode by
configuring the SPI/
I2C
pin to a logic 0. The device is connected to this bus as slave devices (i.e., no clock is generated
by the AD5380/81/82/83). The AD5380 has a 7-bit slave address 1010 1AD1AD0. The 5 MSBs are hard coded and the
two LSBs are determined by the state of the AD1 AD0 pins.The facility to hardware configure AD1 and AD0 allows
four of these devices to be configured on the bus.
I2C Data Transfer
One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of
the SCL clock pulse. Changes in SDA while SCL is high are control signals that configure START and STOP Condi-
tions. Both SDA and SCL are pulled high by the external pull-up resistors when the I
2
C bus is not busy.
START and STOP Conditions
A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high. A START condition
from the master signals the beginning of a transmission to the AD5380. The STOP condition frees the bus. If a repeated
START condition (S
r
) is generated instead of a STOP condition, the bus remains active.
Repeated START Conditions
A repeated START (S
r
) condition may indicate a change of data direction on the bus. S
r
may be used when the bus mas-
ter is writing to several I
2
C devices and does not want to relinquish control of the bus.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving
device. The AD5380 devices generate an ACK when receiving an address or data by pulling SDA low during the ninth
clock period. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if
a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master
should reattempt communication.
AD5380 Slave Addresses
A bus master initiates communication with a slavedevice by issuing a START condition followed by the 7-
bit slave address. When idle, the AD5380 waits for a START condition followed by its slave address. The LSB of the
address word is the Read/Write (R/
W
) bit. The AD538X devices are receive devices only and when communicating with
these R/
W
= 0. After receiving the proper address
1010 1AD1AD0
, the AD5380 issues an ACK by pulling SDA low for
one clock cycle.
The AD5380 has four different user programmable addresses determined by the AD1 and AD0 bits.
Write Operation
There are three specific modes in which data can be written to the AD5380 family of DACs.
4-Byte Mode.
When writing to the AD5380 DACs, the user must begin with an address byte (R/
W
= 0) after which the DAC will ac-
knowledge that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte,
this addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. Two bytes of
data are then written to the DAC as shown in Figure 11. A STOP condition follows. This allows the user to update a single
channel within the AD5380 at any time and requires 4 bytes of data to be transferred from the master.
Figure 11 . 4-Byte AD5380, I2C Write Operation
0
0
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
1
0
1
0
1
AD0
R/
W
A0
ACK
BY
AD538X
ACK
BY
AD538X
MSB
ADDRESS BYTE
START
COND
BY
MASTER
SCL
SDA
SCL
SDA
REG1
LSB
MSB
LSB
ACK
BY
AD538X
ACK
BY
AD538X
STOP
COND
BY
MASTER
POINTER BYTE
AD1
A5
A4
A3
A2
A1
REG0
MSB
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