參數(shù)資料
型號(hào)： AD5380BST-3
廠商： ANALOG DEVICES INC
元件分類(lèi)： DAC
英文描述： 40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC
中文描述： PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100
封裝： 14 X 14 MM, MS-026BED, LQFP-100
文件頁(yè)數(shù)： 18/34頁(yè)
文件大小： 975K
代理商： AD5380BST-3
PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
–18–
AD5380
AD5380 On-chip Special Function Registers (SFR)
The AD5380 contains a number of special function registers (SFRs)as outlined in table V. SFRs are addressed with
REG1=REG0= 0 and are decoded using the Address bits A5 to A0.
Table V. SFR Register Functions (REG1 =0, REG0 = 0)
R/
W
X
0
0
0
0
0
1
0
0
A5 A4 A3 A2 A1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0
0
1
0
0
1
0
0
0
1
Function
NOP (No Operation)
Write ClR Code
Soft CLR
Soft Power Down
Soft Power Up
Control Register Write
Control Register Read
Monitor Channel
Soft Reset
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
SFR Commands
NOP
(no operation)
REG1=REG0=0, A5-A0=000000
Performs no operation but is useful in readback mode to clock out data on Dout for diagnostic purposes.
BUSY
pulses
low during a NOP operation.
Write CLR Code
REG1=REG0=0, A5-A0=000001
DB13-DB0= Contain the CLR data.
Bringing the
CLR
line low or exercising the soft clear function will load the contents of the DAC registers with the data
contained in the user configurable CLR register and sets VOUT0-VOUT39 accordingly. This can be very useful not
only for setting up a specific output voltage in a clear condition but can also be used for calibration purposes where the
user can load fullscale or zeroscale to the the clear code register and then issue a hardware or software clear to load this
code to all DAC removing the need for individual writes to all DACs. Default on power up is all zeroes.
Soft CLR
REG1=REG0=0, A5-A0=000010
DB13-DB0= Dont Care.
Executing this instruction performs the CLR which is functionally the same as that provided by the external CLR pin.
The DAC outputs are loaded with the data in the CLR code register. The time taken to fully execute the SOFT CLR is
80*400ns and is indicated by the
BUSY
low time.
Soft Power Down
REG1=REG0=0, A5-A0=001000
DB13-DB0= Dont Care.
Executing this instruction performs a global power-down feature that puts all channels into a low power mode reducing
both analog and digital power consumption to 5uA. In power down mode the output amplifier can be configured as a
high impedance output or provide a 100k load to ground. The contents of all internal registers are retained in power-
down mode. Cannot write to any register while in power down.
Soft Power up
REG1=REG0=0, A5-A0=001001
DB13-DB0= Dont Care.
This instruction is used to power up the output amplifiers and internal reference. The time to exit power down is XXus.
The hardware power down and software function are internally combined in a digital OR function.
Soft RESET
REG1=REG0=0, A5-A0=001111
DB13-DB0= Dont Care.
This instruction is used to implement a software reset. All internal registers are reset to their default values which corre-
sponds to m at fullscale and c at zero. The contents of the DAC registers are cleared setting all analog outputs to zero
volts. The soft reset activation time is 150us (typ).
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